Patents by Inventor Sota MATSUMOTO
Sota MATSUMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953924Abstract: In order to prevent unnatural behavior of a calculated flow rate, provided is a fluid control device in which a fluid control valve and upstream and downstream pressure sensors are provided on a flow path. The device includes a calculation unit configured to calculate a flow rate based on measured pressures; and an output unit configured to output the calculated flow rate, and exhibit a zero output function of outputting a zero value regardless of the calculated flow rate when the valve is in a closed state. The device is further configured to switch between execution and stop of the zero output function, and when the valve is in an open state and a difference between the measured pressures of the pressure sensors is larger than a threshold, stop the zero output function and cause the flow rate output unit to output the calculated flow rate.Type: GrantFiled: June 23, 2022Date of Patent: April 9, 2024Assignee: HORIBA STEC, Co., Ltd.Inventors: Sota Matsumoto, Kentaro Nagai, Yosuke Hisamori, Kazuhiro Matsuura
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Publication number: 20230229177Abstract: A fluid control device includes a fluid resistance element provided to a channel, an upstream pressure sensor configured to detect an upstream pressure of the fluid resistance element, a downstream pressure sensor configured to detect a downstream pressure of the fluid resistance element, a flow rate calculating unit configured to calculate a flow rate flowing through the channel based on the upstream and downstream pressures, a valve provided upstream of the upstream pressure sensor or downstream of the downstream pressure sensor, and a valve control unit configured to control the valve based on the calculated flow rate. When the valve is fully closed, the flow rate calculating unit is configured to calculate the flow rate by switching a first flow rate calculation formula that is used when the valve is open, to a second flow rate calculation formula that is different from the first flow rate calculation formula.Type: ApplicationFiled: December 28, 2022Publication date: July 20, 2023Inventors: Kentaro NAGAI, Kazuhiro MATSUURA, Yoshiki MIYATA, Sota MATSUMOTO, Yosuke HISAMORI
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Patent number: 11609146Abstract: In order to accurately judge whether or not there is a seat leakage in the first valve and the second valve in a short period of time, a fluid control apparatus comprises a fluid resistor arranged in a flow channel, a first valve arranged upstream of the fluid resistor, a first pressure sensor that measures a pressure in a first volume between the first valve and the fluid resistor in the flow channel, a second valve arranged downstream of the fluid resistor, a second pressure sensor that measures a pressure in a second volume between the fluid resistor and the second valve, a valve controller that controls the first or second valve, and a seat leakage judging part that judges whether or not there is a seat leakage in the valve valves based on the pressure sensors in a state where the valves are fully closed.Type: GrantFiled: March 11, 2020Date of Patent: March 21, 2023Assignee: HORIBA STEC, Co., Ltd.Inventors: Sota Matsumoto, Kentaro Nagai, Yuko Imasato
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Patent number: 11594549Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region. The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer.Type: GrantFiled: March 16, 2021Date of Patent: February 28, 2023Assignee: Kioxia CorporationInventors: Ayumi Watarai, Taichi Iwasaki, Osamu Matsuura, Yu Hirotsu, Sota Matsumoto
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Publication number: 20220413521Abstract: In order to prevent unnatural behavior of a calculated flow rate, provided is a fluid control device in which a fluid control valve and upstream and downstream pressure sensors are provided on a flow path. The device includes a calculation unit configured to calculate a flow rate based on measured pressures; and an output unit configured to output the calculated flow rate, and exhibit a zero output function of outputting a zero value regardless of the calculated flow rate when the valve is in a closed state. The device is further configured to switch between execution and stop of the zero output function, and when the valve is in an open state and a difference between the measured pressures of the pressure sensors is larger than a threshold, stop the zero output function and cause the flow rate output unit to output the calculated flow rate.Type: ApplicationFiled: June 23, 2022Publication date: December 29, 2022Inventors: Sota MATSUMOTO, Kentaro NAGAI, Yosuke HISAMORI, Kazuhiro MATSUURA
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Publication number: 20220302155Abstract: A semiconductor memory device according to an embodiment includes: a first stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, the first stacked body including a stair portion processed into a stair shape extending in a first direction such that the plurality of conductive layers forms terrace surfaces; an insulating film covering an upper portion of the first stacked body including the stair portion; and a first plate-like portion that extends in the first direction in the stair portion and penetrates the first stacked body, the first plate-like portion including a plurality of bridge portions that are arranged locally on an upper end portion side and intermittently in the first direction to couple parts of the insulating film arranged on both sides of the first plate-like portion to each other.Type: ApplicationFiled: September 3, 2021Publication date: September 22, 2022Applicant: Kioxia CorporationInventors: Ayumi WATARAI, Osamu MATSUURA, Taro KUSUMOTO, Sota MATSUMOTO
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Publication number: 20220130829Abstract: A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory region in which a plurality of memory cells are disposed and a staircase region in which end portions of the plurality of conductive layers form a staircase shape. A first region of the staircase region includes a first sub-staircase portion ascending in a first direction toward the memory portion, and a second sub-staircase portion disposed side by side with the first sub-staircase portion in a second direction opposite to the first direction from the first sub-staircase portion and ascending in the second direction.Type: ApplicationFiled: January 6, 2022Publication date: April 28, 2022Applicant: Kioxia CorporationInventors: Sota MATSUMOTO, Takahito NISHIMURA
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Publication number: 20220085052Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region. The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer.Type: ApplicationFiled: March 16, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Ayumi WATARAI, Taichi IWASAKI, Osamu MATSUURA, Yu HIROTSU, Sota MATSUMOTO
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Patent number: 11264387Abstract: A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory portion in which a plurality of memory cells are disposed and a staircase portion in which end portions of the plurality of conductive layers form a staircase shape. The staircase portion has three or more first sub-staircase portions ascending in a direction opposite to a direction toward the memory portion, and at least one first sub-staircase portion among the three or more first sub-staircase portions is divided into at least an upper staircase and a lower staircase by a difference in level larger than a difference in level of each stair of the first sub-staircase portion.Type: GrantFiled: March 5, 2020Date of Patent: March 1, 2022Assignee: Kioxia CorporationInventors: Sota Matsumoto, Takahito Nishimura
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Publication number: 20210066297Abstract: A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory portion in which a plurality of memory cells are disposed and a staircase portion in which end portions of the plurality of conductive layers form a staircase shape. The staircase portion has three or more first sub-staircase portions ascending in a direction opposite to a direction toward the memory portion, and at least one first sub-staircase portion among the three or more first sub-staircase portions is divided into at least an upper staircase and a lower staircase by a difference in level larger than a difference in level of each stair of the first sub-staircase portion.Type: ApplicationFiled: March 5, 2020Publication date: March 4, 2021Applicant: Kioxia CorporationInventors: Sota Matsumoto, Takahito Nishimura
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Publication number: 20200292407Abstract: In order to accurately judge whether or not there is a seat leakage in the first valve and the second valve in a short period of time, a fluid control apparatus comprises a fluid resistor arranged in a flow channel, a first valve arranged upstream of the fluid resistor, a first pressure sensor that measures a pressure in a first volume between the first valve and the fluid resistor in the flow channel, a second valve arranged downstream of the fluid resistor, a second pressure sensor that measures a pressure in a second volume between the fluid resistor and the second valve, a valve controller that controls the first or second valve, and a seat leakage judging part that judges whether or not there is a seat leakage in the valve valves based on the pressure sensors in a state where the valves are fully closed.Type: ApplicationFiled: March 11, 2020Publication date: September 17, 2020Inventors: Sota Matsumoto, Kentaro Nagai, Yuko Imasato
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Publication number: 20200251490Abstract: A semiconductor memory device according to an embodiment includes, a stacked portion and a pillar. The stacked portion is provided in a first region including a memory cell and in a second region. The stacked portion includes first and second conductive layers and a first insulating layer. The first conductive layers are stacked in a first direction. The second conductive layers are stacked in the first direction above the first conductive layers. The first insulating layer is provided between an uppermost first conductive layer and a lowermost second conductive layer. The pillar penetrates the first and second conductive layers and the first insulating layer.Type: ApplicationFiled: July 26, 2019Publication date: August 6, 2020Applicant: Toshiba Memory CorporationInventors: Sota MATSUMOTO, Junichi SHIBATA, Takahito NISHIMURA, Kazuhiro WASHIDA