Abstract: A processor includes an operation executer configured to execute pipeline processing of an operation instruction, wherein the operation executer includes a first register configured to hold data to be used for an operation; a pre-processor configured to pre-process data held in the first register; a second register configured to hold the data pre-processed by the pre-processor; an operator configured to execute an operation on the data held in the first register or the data held in the second register; and a selector configured to connect an output of the first register or an output of the second register to an input of the operator.

Abstract: An arithmetic processing device includes an instruction storage configured to store an arithmetic instruction and a data cache configured to cache a calculation result of the arithmetic instruction. A plurality of floating-point registers arranged on a side of the instruction storage is configured to store a register value used for executing the arithmetic instruction transferred from the instruction storage, and a plurality of floating point calculation circuits arranged on a side of the data cache is configured to perform a floating-point operation based on the arithmetic instruction, wherein a number of cycles is one when the register value is transferred from the instruction storage to one or more floating-point registers, among the plurality of floating point registers, arranged in positions closest in distance to the instruction storage.

Abstract: An arithmetic processing apparatus includes an instruction execution control circuit that outputs an instruction from an entry of entries, including an executable instruction information storage circuit storing executable instruction information indicating whether an instruction in each of the entries is executable, a priority information storage circuit including, for each entry, storage areas storing priority information indicating whether an instruction in an entry has higher priority on an entry-by-entry basis, an executable instruction information write circuit writing the executable instruction information in response to determining whether an instruction in each of the entries is executable, a priority information write circuit writing the priority information in response to determining whether an instruction in each of the entries has higher priority, and an output determination circuit selecting an entry from which an instruction is output on a basis of the executable instruction information and the

Abstract: An arithmetic processing device includes, an arithmetic circuit capable of operating as a plurality of sub arithmetic circuits according to a bit width of data to be calculated, and a plurality of registers each including a plurality of subregions that corresponds to the plurality of sub arithmetic circuits respectively. The device further includes a mask circuit that masks, when an operation that uses a part of the plurality of sub arithmetic circuits is executed, storage of invalid operation result data output from the sub arithmetic circuit that does not receive data to be subject to the operation in the subregion; and a data replacement circuit that replaces data, output from the subregion in which the storage is masked, with a zero-value to output the zero-value to the arithmetic circuit when the operation that uses the data retained in the register that includes the subregion in which the storage is masked.

Abstract: A calculation processing apparatus includes a decoder that decodes memory access instructions including a store instruction and a load instruction; a first queue that stores the decoded memory access instructions; a second queue that stores store data related to the store instruction; a storage circuit that stores target address information of the store instruction for which the first queue is reserved but the second queue is not reserved; and an inhibitor that inhibits execution of the load instruction when address information matching target address information of the load instruction is stored in the storage circuit when the load instruction is being processed. This configuration inhibits switching of the order of a store instruction and a load instruction.

Abstract: An arithmetic processing device includes: a decoding circuit configured to decode a command; a command execution circuit configured to execute the command decoded by the decoding circuit; a register circuit configured to include a plurality of registers for holding data used by the command execution circuit; an identification information holding circuit configured to store identification information for identifying a register for writing a specific value when the command is a register writing command; a setting circuit configured to hold the specific value; and an operation control circuit configured to execute inhibiting processing when the command is a register reading command, the inhibiting processing including inhibiting an access of the register by the register reading command and selecting the specific value held in the setting circuit.

Abstract: A processing apparatus includes a processor. The processor stores a plurality of instruction codes, each of the plurality of instruction codes is a result of decoding of an instruction, selects an instruction code that is ready to be input from the stored instruction codes, when the selected instruction code is an operation instruction, uses for the processing, a register for processing corresponding to a write destination of the operation instruction, after detecting that operands to be used for the processing are ready, in the next cycle, issues a subsequent instruction, and when the selected instruction code is a memory access instruction, uses for the address calculation, the register, writes a processing result and load data that have been temporarily written in a buffer for register update from the buffer to the register at the time of instruction completion, after the completion of the memory access instruction, issues a subsequent instruction.

Abstract: By including a storing device that stores a plurality of memory access instructions decoded by a decoder and outputs the memory access instruction stored therein to a cache memory, a determiner that determines whether the storing device is afford to store the plurality of memory access instructions; and an inhibitor that inhibits, when the determiner determines that the storing device is not afford to store a first memory access instruction included in the plurality of memory access instructions, execution of a second memory access instruction being included in the plurality of memory access instructions and being subsequent to the first memory access instruction for a predetermined time period, regardless of a result of determination made on the second memory access instruction by the determiner, the calculation processing apparatus inhibits a switch of the order of a store instruction and a load instruction.

Abstract: An operation processing device includes a first register unit including first registers configured to hold data to be used for an operation in an operation unit; a first selection unit that selects data held by a first register indicated by a read address signal; a second selection unit that selects, based on a bypass selection signal, data from a data group including the data selected by the first selection unit and data indicative of a result of the operation; a second register unit that outputs the data selected by the second selection unit to the operation unit; a timing adjustment unit that outputs the read address signal to the first selection unit; and a bypass control unit that stops an operation of the timing adjustment unit when generating the bypass selection signal indicative of a selection of data other than the data selected by the first selection unit.

Abstract: A Load and Store Queue (LDSTQ) stores load store instructions therein with an upper limit being a first number, and sequentially outputs the stored load store instructions to cause a data cache or a main memory to execute processing of data in accordance with the output load store instructions. A decode unit acquires load store instructions, and determines a queued number of load store instructions which have not been output from the LDSTQ among load store instructions output from the decode unit. When the queued number is smaller than a second number which is larger than the first number, the decode unit outputs the acquired load store instructions. An LDSTQ management unit acquires the output load store instructions. When the stored number of load store instructions stored in the LDSTQ is smaller than the first number, the LDSTQ management unit stores the acquired load store instructions in the LDSTQ.

Abstract: A calculation processing apparatus includes a decoder that decodes memory access instructions including a store instruction and a load instruction; a first queue that stores the decoded memory access instructions; a second queue that stores store data related to the store instruction; a storage circuit that stores target address information of the store instruction for which the first queue is reserved but the second queue is not reserved; and an inhibitor that inhibits execution of the load instruction when address information matching target address information of the load instruction is stored in the storage circuit when the load instruction is being processed. This configuration inhibit switching of the order of a store instruction and a load instruction.

Abstract: An arithmetic processing apparatus includes an instruction execution control circuit that outputs an instruction from an entry of entries, including an executable instruction information storage circuit storing executable instruction information indicating whether an instruction in each of the entries is executable, a priority information storage circuit including, for each entry, storage areas storing priority information indicating whether an instruction in an entry has higher priority on an entry-by-entry basis, an executable instruction information write circuit writing the executable instruction information in response to determining whether an instruction in each of the entries is executable, a priority information write circuit writing the priority information in response to determining whether an instruction in each of the entries has higher priority, and an output determination circuit selecting an entry from which an instruction is output on a basis of the executable instruction information and the

Abstract: By including a storing device that stores a plurality of memory access instructions decoded by a decoder and outputs the memory access instruction stored therein to a cache memory, a determiner that determines whether the storing device is afford to store the plurality of memory access instructions; and an inhibitor that inhibits, when the determiner determines that the storing device is not afford to store a first memory access instruction included in the plurality of memory access instructions, execution of a second memory access instruction being included in the plurality of memory access instructions and being subsequent to the first memory access instruction for a predetermined time period, regardless of a result of determination made on the second memory access instruction by the determiner, the calculation processing apparatus inhibits a switch of the order of a store instruction and a load instruction.

Abstract: An arithmetic processing device includes: a decoding circuit configured to decode a command; a command execution circuit configured to execute the command decoded by the decoding circuit; a register circuit configured to include a plurality of registers for holding data used by the command execution circuit; an identification information holding circuit configured to store identification information for identifying a register for writing a specific value when the command is a register writing command; a setting circuit configured to hold the specific value; and an operation control circuit configured to execute inhibiting processing when the command is a register reading command, the inhibiting processing including inhibiting an access of the register by the register reading command and selecting the specific value held in the setting circuit.

Abstract: A processing apparatus includes a processor. The processor stores a plurality of instruction codes, each of the plurality of instruction codes is a result of decoding of an instruction, selects an instruction code that is ready to be input from the stored instruction codes, when the selected instruction code is an operation instruction, uses for the processing, a register for processing corresponding to a write destination of the operation instruction, after detecting that operands to be used for the processing are ready, in the next cycle, issues a subsequent instruction, and when the selected instruction code is a memory access instruction, uses for the address calculation, the register, writes a processing result and load data that have been temporarily written in a buffer for register update from the buffer to the register at the time of instruction completion, after the completion of the memory access instruction, issues a subsequent instruction.

Abstract: An arithmetic processing device includes: a decode circuit configured to decode instructions; an execution control circuit configured to hold the instructions decoded by the decode circuit and to output the held instructions in an executable order; an instruction transfer circuit configured to sequentially transfer the instructions sequentially output by the execution control circuit; an instruction generation circuit configured to output, to the instruction transfer circuit, an individual instruction generated from a combined instruction in a case where one of the instructions transferred by the instruction transfer circuit is the combined instruction obtained by combining individual instructions; and an arithmetic execution circuit configured to execute the individual instruction transferred by the instruction transfer circuit.

Abstract: A Load and Store Queue (LDSTQ) stores load store instructions therein with an upper limit being a first number, and sequentially outputs the stored load store instructions to cause a data cache or a main memory to execute processing of data in accordance with the output load store instructions. A decode unit acquires load store instructions, and determines a queued number of load store instructions which have not been output from the LDSTQ among load store instructions output from the decode unit. When the queued number is smaller than a second number which is larger than the first number, the decode unit outputs the acquired load store instructions. An LDSTQ management unit acquires the output load store instructions. When the stored number of load store instructions stored in the LDSTQ is smaller than the first number, the LDSTQ management unit stores the acquired load store instructions in the LDSTQ.

Abstract: An arithmetic processing device includes an instruction decode unit, an instruction execution unit and an instruction hold unit, wherein the instruction hold unit includes; a first holder including a plurality of first entries each configured to hold a decoded instruction; a second holder including a smaller number of second entries than the number of the first entries; a first selector configured to select an instruction to be registered in the second holder from instructions held in the first entries and store identification information that identifies the selected instruction into any of the second entries; and a second selector configured to sequentially select an executable instruction from instructions registered in the second holder, input the selected executable instruction to the instruction execution unit, and detect a dependency between the instruction inputted to the instruction execution unit and the instructions registered in the second holder.

Abstract: An arithmetic processing device includes: a decode circuit configured to decode instructions; an execution control circuit configured to hold the instructions decoded by the decode circuit and to output the held instructions in an executable order; an instruction transfer circuit configured to sequentially transfer the instructions sequentially output by the execution control circuit; an instruction generation circuit configured to output, to the instruction transfer circuit, an individual instruction generated from a combined instruction in a case where one of the instructions transferred by the instruction transfer circuit is the combined instruction obtained by combining individual instructions; and an arithmetic execution circuit configured to execute the individual instruction transferred by the instruction transfer circuit.

Abstract: An arithmetic processing device includes an instruction decode unit, an instruction execution unit and an instruction hold unit, wherein the instruction hold unit includes; a first holder including a plurality of first entries each configured to hold a decoded instruction; a second holder including a smaller number of second entries than the number of the first entries; a first selector configured to select an instruction to be registered in the second holder from instructions held in the first entries and store identification information that identifies the selected instruction into any of the second entries; and a second selector configured to sequentially select an executable instruction from instructions registered in the second holder, input the selected executable instruction to the instruction execution unit, and detect a dependency between the instruction inputted to the instruction execution unit and the instructions registered in the second holder.