Patents by Inventor Sotaro Ohara
Sotaro Ohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240148368Abstract: A calculator calculates an actual transfer rate of a frame sequence by a communication unit. A determiner determines that frame congestion occurs in a case where the actual transfer rate is lower than a frame rate. A frame rate controller matches the frame rate with the actual transfer rate. As a result, the frame congestion is eliminated. The frame congestion may be eliminated by lowering a load on a processing section.Type: ApplicationFiled: November 2, 2023Publication date: May 9, 2024Applicant: FUJIFILM Healthcare CorporationInventor: SOTARO OHARA
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Publication number: 20240114431Abstract: A communication apparatus in a multi-hop relay system in which a packet is transmitted and received using a flooding method in a first flooding slot and a second flooding slot each including a plurality of sub-slots, the communication apparatus performs: switching a frequency channel to be used to transmit and receive a packet between a first sub-slot and a second sub-slot in the first flooding slot; and not switching the frequency channel to be used to transmit and receive a packet within the second flooding slot, but switching the frequency channel to be used to transmit and receive a packet between a plurality of the second flooding slots.Type: ApplicationFiled: December 13, 2023Publication date: April 4, 2024Applicant: Sonas, Inc.Inventors: Makoto SUZUKI, Sotaro OHARA
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Patent number: 11909525Abstract: There is provided a communication system for performing communication by flooding using concurrent transmission among a plurality of communication nodes including a transmission node, a relay node, and a destination node. The transmission node generates and transmits the packet including predetermined transmission data, a first error detection code for the transmission data, and a second error detection code for the transmission data, timing information corresponding to a transmission timing of the packet, and the first error detection code. The relay node receives the packet, performs error detection based on the second error detection code, and updates the second error detection code and reconstructs and transmits the packet if no error is detected. The destination node receives the packet, and performs error detection based on the first error detection code.Type: GrantFiled: December 6, 2021Date of Patent: February 20, 2024Assignee: SONAS, INC.Inventors: Sotaro Ohara, Makoto Suzuki
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Patent number: 11659509Abstract: There is provided a multi-hop relay system including a transmission node and a relay node, communicating using a flooding method. The transmission node is configured to transmit a synchronization packet used to synchronize a plurality of relay nodes. The relay node is configured to perform first reception in a first period at every first cycle corresponding to the predetermined cycle, and second reception in a second period not less than a length of the predetermined period at every second cycle longer than the first cycle. The relay node performs the second reception if the synchronization packet cannot be received by the first reception, and if the synchronization packet is received by the second reception, stops the second reception and performs the first reception if the predetermined condition is determined to be satisfied, and if not, executes synchronization recovery processing.Type: GrantFiled: November 4, 2022Date of Patent: May 23, 2023Assignee: SONAS, INC.Inventors: Sotaro Ohara, Makoto Suzuki
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Publication number: 20230058590Abstract: There is provided a multi-hop relay system including a transmission node and a relay node, communicating using a flooding method. The transmission node is configured to transmit a synchronization packet used to synchronize a plurality of relay nodes. The relay node is configured to perform first reception in a first period at every first cycle corresponding to the predetermined cycle, and second reception in a second period not less than a length of the predetermined period at every second cycle longer than the first cycle. The relay node performs the second reception if the synchronization packet cannot be received by the first reception, and if the synchronization packet is received by the second reception, stops the second reception and performs the first reception if the predetermined condition is determined to be satisfied, and if not, executes synchronization recovery processing.Type: ApplicationFiled: November 4, 2022Publication date: February 23, 2023Applicant: SONAS, INC.Inventors: Sotaro OHARA, Makoto SUZUKI
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Publication number: 20220094475Abstract: There is provided a communication system for performing communication by flooding using concurrent transmission among a plurality of communication nodes including a transmission node, a relay node, and a destination node. The transmission node generates and transmits the packet including predetermined transmission data, a first error detection code for the transmission data, and a second error detection code for the transmission data, timing information corresponding to a transmission timing of the packet, and the first error detection code. The relay node receives the packet, performs error detection based on the second error detection code, and updates the second error detection code and reconstructs and transmits the packet if no error is detected. The destination node receives the packet, and performs error detection based on the first error detection code.Type: ApplicationFiled: December 6, 2021Publication date: March 24, 2022Applicant: SONAS, INC.Inventors: Sotaro OHARA, Makoto SUZUKI
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Patent number: 10591953Abstract: The present disclosure relates to a signal processing apparatus and method that enables to reduce required power. In the signal processing apparatus, a RTC of a main chip and a RTC of a power supply chip are synchronized before power supply of the main chip is stopped, and the RTC of the main chip is synchronized with the time of the RTC of the power supply chip after the power supply of the main chip is restored. In this way, the RTC uses continuous time information before and after the stop. The present disclosure is capable of being applied to, for example, a GPS module in which a digital circuit includes a plurality of chips.Type: GrantFiled: May 20, 2016Date of Patent: March 17, 2020Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Sotaro Ohara, Katsuyuki Tanaka, Katsumi Takaoka, Keita Izumi, Suguru Houchi, Gaku Hidai, Yutaka Takagi, Hideki Takahashi, Hideki Awata, Yasushi Katayama, Naoki Yoshimochi, Toshimasa Shimizu
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Publication number: 20180210487Abstract: The present disclosure relates to a signal processing apparatus and method that enables to reduce required power. In the signal processing apparatus, a RTC of a main chip and a RTC of a power supply chip are synchronized before power supply of the main chip is stopped, and the RTC of the main chip is synchronized with the time of the RTC of the power supply chip after the power supply of the main chip is restored. In this way, the RTC uses continuous time information before and after the stop. The present disclosure is capable of being applied to, for example, a GPS module in which a digital circuit includes a plurality of chips.Type: ApplicationFiled: May 20, 2016Publication date: July 26, 2018Inventors: SOTARO OHARA, KATSUYUKI TANAKA, KATSUMI TAKAOKA, KEITA IZUMI, SUGURU HOUCHI, GAKU HIDAI, YUTAKA TAKAGI, HIDEKI TAKAHASHI, HIDEKI AWATA, YASUSHI KATAYAMA, NAOKI YOSHIMOCHI, TOSHIMASA SHIMIZU
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Patent number: 9900854Abstract: There is provided a signal processing device including a selection unit that selects and outputs one clock serving as a transport stream (TS) clock, which represents timing of data of a TS, among a plurality of clocks with frequencies not less than a serial rate which is a data rate at which the TS included in a radio frequency (RF) signal is output in a serial manner.Type: GrantFiled: May 23, 2013Date of Patent: February 20, 2018Assignee: Saturn Licensing LLCInventors: Yuichi Hirayama, Satoshi Okada, Yuichi Mizutani, Sotaro Ohara
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Publication number: 20150139220Abstract: There is provided a signal processing device including a selection unit that selects and outputs one clock serving as a transport stream (TS) clock, which represents timing of data of a TS, among a plurality of clocks with frequencies not less than a serial rate which is a data rate at which the TS included in a radio frequency (RF) signal is output in a serial manner.Type: ApplicationFiled: May 23, 2013Publication date: May 21, 2015Inventors: Yuichi Hirayama, Satoshi Okada, Yuichi Mizutani, Sotaro Ohara
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Publication number: 20150131746Abstract: Provided is a signal processing device, including a clock width calculation unit configured to calculate a clock width corresponding to a data rate of a valid section in which a transport stream (TS) packet exists, and a generation unit configured to generate a clock signal whose period is the clock width calculated in the clock width calculation unit and to output the clock signal as a shaped TS clock signal, the shaped TS clock signal being a TS clock signal of the TS packet to which shaping has been performed.Type: ApplicationFiled: May 20, 2013Publication date: May 14, 2015Applicant: Sony CorporationInventors: Yuichi Hirayama, Satoshi Okada, Sotaro Ohara, Yuichi Mizutani