Patents by Inventor Sou Hoshi
Sou Hoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9345126Abstract: A substrate of a semiconductor package comprises a conductor pattern which is formed in a surface layer, and is electrically connected to one terminal out of a power terminal and a ground terminal of a semiconductor element. The substrate also comprises in the surface layer a conductor pattern which is arranged while being separated from the conductor pattern, and a conductor pattern which is formed so as to have a wiring width thinner than that of the conductor pattern and connects the conductor pattern with the conductor pattern. The substrate also comprises a conductor pattern which is formed in an inner layer, faces the conductor pattern through a dielectric and is electrically connected to the other terminal out of the power terminal and the ground terminal of the semiconductor element.Type: GrantFiled: March 6, 2014Date of Patent: May 17, 2016Assignee: CANON KABUSHIKI KAISHAInventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai
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Patent number: 9326370Abstract: Provided is a printed circuit board capable of increasing an inductance value of a power pattern and a ground pattern while keeping a low electric resistance value of the power pattern and the ground pattern. The printed circuit board includes a printed wiring board including: a power layer having a power pattern formed therein; and a ground layer having a ground pattern formed therein. On the printed wiring board, an LSI as a semiconductor device and an LSI as a power supply member are mounted. The ground pattern has a first ground region that overlaps the power pattern as viewed from the direction perpendicular to the surface of the printed wiring board. In the first ground region, at least one defect portion is formed. In the first ground region, the defect portion forms a region that is narrower than the power pattern.Type: GrantFiled: March 28, 2013Date of Patent: April 26, 2016Assignee: CANON KABUSHIKI KAISHAInventors: Yusuke Murai, Sou Hoshi, Nobuaki Yamashita
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Patent number: 9252098Abstract: A semiconductor apparatus includes a multilayer interposer substrate including a power layer as an inner layer; a plurality of connection terminals provided on one surface of the interposer substrate; and a semiconductor chip mounted on the other surface of the interposer substrate. Among power terminals, ground terminals, and signal terminals provided in the semiconductor apparatus, all the power terminals are arranged in one power area and the power area includes only the power terminals.Type: GrantFiled: November 2, 2010Date of Patent: February 2, 2016Assignee: CANON KABUSHIKI KAISHAInventor: Sou Hoshi
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Patent number: 9084364Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.Type: GrantFiled: June 12, 2013Date of Patent: July 14, 2015Assignee: CANON KABUSHIKI KAISHAInventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai, Tohru Ohsaka
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Publication number: 20140268586Abstract: A substrate of a semiconductor package comprises a conductor pattern which is formed in a surface layer, and is electrically connected to one terminal out of a power terminal and a ground terminal of a semiconductor element. The substrate also comprises in the surface layer a conductor pattern which is arranged while being separated from the conductor pattern, and a conductor pattern which is formed so as to have a wiring width thinner than that of the conductor pattern and connects the conductor pattern with the conductor pattern. The substrate also comprises a conductor pattern which is formed in an inner layer, faces the conductor pattern through a dielectric and is electrically connected to the other terminal out of the power terminal and the ground terminal of the semiconductor element.Type: ApplicationFiled: March 6, 2014Publication date: September 18, 2014Applicant: CANON KABUSHIKI KAISHAInventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai
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Publication number: 20130343024Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.Type: ApplicationFiled: June 12, 2013Publication date: December 26, 2013Inventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai, Tohru Ohsaka
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Publication number: 20130265726Abstract: Provided is a printed circuit board capable of increasing an inductance value of a power pattern and a ground pattern while keeping a low electric resistance value of the power pattern and the ground pattern. The printed circuit board includes a printed wiring board including: a power layer having a power pattern formed therein; and a ground layer having a ground pattern formed therein. On the printed wiring board, an LSI as a semiconductor device and an LSI as a power supply member are mounted. The ground pattern has a first ground region that overlaps the power pattern as viewed from the direction perpendicular to the surface of the printed wiring board. In the first ground region, at least one defect portion is formed. In the first ground region, the defect portion forms a region that is narrower than the power pattern.Type: ApplicationFiled: March 28, 2013Publication date: October 10, 2013Applicant: CANON KABUSHIKI KAISHAInventors: Yusuke Murai, Sou Hoshi, Nobuaki Yamashita
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Publication number: 20120211897Abstract: A semiconductor apparatus includes a multilayer interposer substrate including a power layer as an inner layer; a plurality of connection terminals provided on one surface of the interposer substrate; and a semiconductor chip mounted on the other surface of the interposer substrate. Among power terminals, ground terminals, and signal terminals provided in the semiconductor apparatus, all the power terminals are arranged in one power area and the power area includes only the power terminals.Type: ApplicationFiled: November 2, 2010Publication date: August 23, 2012Applicant: CANON KABUSHIKI KAISHAInventor: Sou Hoshi
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Patent number: 7408209Abstract: Radiation noise is reduced, and any operation error is prevented by suppressing noise propagation between an input/output circuit and an internal circuit while preventing or minimizing an increase in the number of steps of semiconductor element design. A semiconductor device having an input/output circuit region and an internal circuit region includes an internal circuit power supply cell which is arranged in the input/output circuit region and supplies a power to the internal circuit region, an internal circuit ground cell which is arranged in the input/output circuit region and supplies ground to the internal circuit region, and noise control cells which are arranged to sandwich the internal circuit power supply cell and the internal circuit ground cell in the input/output circuit region and formed by electrically connecting a p-type semiconductor substrate to ground independently of the input/output circuit region and the internal circuit region.Type: GrantFiled: December 14, 2005Date of Patent: August 5, 2008Assignee: Canon Kabushiki KaishaInventor: Sou Hoshi
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Publication number: 20060131727Abstract: Radiation noise is reduced, and any operation error is prevented by suppressing noise propagation between an input/output circuit and an internal circuit while preventing or minimizing an increase in the number of steps of semiconductor element design. A semiconductor device having an input/output circuit region and an internal circuit region includes an internal circuit power supply cell which is arranged in the input/output circuit region and supplies a power to the internal circuit region, an internal circuit ground cell which is arranged in the input/output circuit region and supplies ground to the internal circuit region, and noise control cells which are arranged to sandwich the internal circuit power supply cell and the internal circuit ground cell in the input/output circuit region and formed by electrically connecting a p-type semiconductor substrate to ground independently of the input/output circuit region and the internal circuit region.Type: ApplicationFiled: December 14, 2005Publication date: June 22, 2006Inventor: Sou Hoshi