Patents by Inventor Souichi Imamura

Souichi Imamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6061026
    Abstract: A high-gain monolithic antenna with high freedom of design has a signal circuit and a stripline dipole antenna which are provided on a substrate. A dielectric film and a conductor cover covering the dielectric film are provided on the upper surface of the substrate, in addition to a hole extending vertically downward to the underside of the substrate, a conductor wall being provided on the surface thereof. Furthermore, a metallic film is evaporated so as to contact both a metallic cover and a conductor wall. A first grounding conductor and a dielectric are provided on the lower surface of the substrate, and a second grounding conductor is provided on the upper surface of the substrate. A horn, which is tapered into the dielectric and the first grounding conductor thereby forming the shape of a quadrangular pyramid, is provided so as to overlap a hole etched into the substrate. Microwaves or milliwaves are radiated to/from the horn to/from the underside of the substrate.
    Type: Grant
    Filed: February 10, 1998
    Date of Patent: May 9, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Ochi, Souichi Imamura, Shigehiro Hosoi, Yutaka Ueno
  • Patent number: 5717232
    Abstract: A semiconductor device has an active layer formed on a semiconductor substrate with different types of junctions, a source region, a drain region, a T-shaped gate electrode in which the cross-sectional area of the upper surface is larger than that of the lower surface, a first dielectric layer covering at least the exposed surface of the active layer, and the gate electrode, and a second dielectric layer enclosing the first dielectric layer. In the device, when the specific inductive capacities of the first and second dielectric layers are .epsilon.(1) and .epsilon.(2) respectively .epsilon.(1)<.epsilon.(2) and the water absorption ratio of the first dielectric layer is greater than the water absorption ratio of the second dielectric layer.
    Type: Grant
    Filed: April 16, 1996
    Date of Patent: February 10, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Inoue, Souichi Imamura, Masanori Ochi, Shigehiro Hosoi, Toru Suga, Takashi Kimura
  • Patent number: 5409849
    Abstract: According to this invention, there is provided a method of manufacturing a compound semiconductor which can be formed at a high yield and in which variations in characteristics of elements caused by variations in distances between a source and a gate and between a drain and the gate can be minimized. In addition, there is provided a compound semiconductor device having a structure capable of increasing a power gain and obtaining a high-speed operation. According to this invention, an active layer is formed on a compound semi-conductor substrate, and source/drain electrodes are formed on the active layer to be separated from each other. The wall insulating films are respectively formed on side walls of the electrodes, and a gate electrode is formed between the side wall insulating films to be respectively in contact therewith.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: April 25, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Kishita, Masanori Ochi, Souichi Imamura, Toshikazu Fukuda
  • Patent number: 5314844
    Abstract: A method of dicing a wafer of III-V compound material without causing chipping and cracks. The method includes the steps of forming a scribe line on a surface of the wafer orthogonal to a crystal plane (011) by means of a scribing method, forming a groove in the semiconductor wafer in parallel to the crystal plane (011) by means of a grinding-cutting method, and breaking the semiconductor wafer along the scribe line and the groove.
    Type: Grant
    Filed: March 4, 1992
    Date of Patent: May 24, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Souichi Imamura
  • Patent number: 5260603
    Abstract: A semiconductor device having a GaAs substrate and an ohmic electrode. An electrode pad is on part of the ohmic electrode and on part of the GaAs substrate outside the ohmic electrode. The electrode pad includes a first platinum film, a titanium film, a second platinum film, and a gold film which are sequentially deposited on one another. The first platinum film is thinner than each of the titanium film, second platinum film and gold film.
    Type: Grant
    Filed: September 8, 1992
    Date of Patent: November 9, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mayumi Kamura, Souichi Imamura, Tatsuo Akiyama
  • Patent number: 5204278
    Abstract: After a silicon nitride film is deposited on a compound semiconductor substrate, another insulating film such as a silicon dioxide film is provided thereon so as to define a channel region in the semiconductor substrate. Impurity ions such as Si ions are selectively implanted into the semiconductor substrate in the presence of the silicon nitride film and the insulating film, thereby providing source and drain regions and the channel region therein. The insulating film and the silicon nitride film located above the channel region are successively removed to provide a Schottky gate electrode thereon. The silicon nitride film is selectively removed from the substrate surface to provide source and drain electrodes on their regions. Accordingly, MESFETs can be produced without exposing the substrate surface during its manufacture.
    Type: Grant
    Filed: March 20, 1992
    Date of Patent: April 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Souichi Imamura, Toru Suga