Patents by Inventor Souichi Nagano

Souichi Nagano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6909179
    Abstract: A semiconductor device includes a substrate, a semiconductor chip mounted on one surface of the substrate, wherein the semiconductor chip has an integrated circuit and bonding pads formed on a main surface thereof. The main surface of the semiconductor chip has a quadrilateral shape with the bonding pads being disposed along four sides of the main surface. A plurality of conductors is disposed on the one surface of the substrate so as to surround the semiconductor chip along four sides thereof and a plurality of bonding wires electrically connect the bonding pads with tips of the conductors, respectively. A resin body seals the semiconductor chip, the conductors and the plurality of bonding wires. A pitch between adjacent bonding pads increases in a direction toward four corners defined by the four sides of the main surface of the semiconductor chip.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: June 21, 2005
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Shigeki Tanaka, Atsushi Fujisawa, Souichi Nagano, Tsugihiko Hirano, Ryouichi Oota, Takafumi Konno, Kenichi Tatebe, Toshiaki Okamoto
  • Publication number: 20010050419
    Abstract: A semiconductor device includes a substrate, a semiconductor chip mounted on one surface of the substrate, wherein the semiconductor chip has an integrated circuit and bonding pads formed on a main surface thereof. The main surface of the semiconductor chip has a quadrilateral shape with the bonding pads being disposed along four sides of the main surface. A plurality of conductors is disposed on the one surface of the substrate so as to surround the semiconductor chip along four sides thereof and a plurality of bonding wires electrically connect the bonding pads with tips of the conductors, respectively. A resin body seals the semiconductor chip, the conductors and the plurality of bonding wires. A pitch between adjacent bonding pads increases in a direction toward four corners defined by the four sides of the main surface of the semiconductor chip.
    Type: Application
    Filed: July 16, 2001
    Publication date: December 13, 2001
    Inventors: Shigeki Tanaka, Atsushi Fujisawa, Souichi Nagano, Tsugihiko Hirano, Ryouichi Oota, Takafumi Konno, Kenichi Tatebe, Toshiaki Okamoto
  • Patent number: 6265762
    Abstract: There is provided a semiconductor chip mounting area for mounting a semiconductor chip, and the points of the inner leads are made to come closer to the semiconductor chip mounting area by arranging the points of the inner leads at equal intervals over the whole periphery of the semiconductor chip mounting area. The points of the inner leads are arranged along the whole periphery of the semiconductor chip mounting area, and the lead pitch at the points of the inner leads corresponding to a corner portion of the semiconductor chip mounting area is made wider than the lead pitch of the other inner lead points.
    Type: Grant
    Filed: March 18, 1997
    Date of Patent: July 24, 2001
    Assignees: Hitachi, LTD, Hitachi Hoakki Semiconductor, LTD
    Inventors: Shigeki Tanaka, Atsushi Fujisawa, Souichi Nagano, Tsugihiko Hirano, Ryouichi Oota, Takafumi Konno, Kenichi Tatebe, Toshiaki Okamoto