Abstract: A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysilicon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

Abstract: A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysiliccon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

Abstract: A transistor element is formed on the surface of a silicon substrate. A tunnel is formed in the silicon substrate at a position right under the transistor element. A contact hole is formed to extend from the surface of the silicon substrate to the contact hole. Silicon oxide films are respectively formed on the inner surfaces of the tunnel and the contact hole. A wiring layer is buried in the tunnel and the contact hole. The wiring layer is connected to a diffusion layer of the transistor element.

Abstract: Disclosed herein is a semiconductor device comprising a semiconductor substrate, a well region provided in the surface of the substrate, a plurality of MOSFETs provided in the well region. The well region has parts having a low surface impurity concentration. Some of the MOSFETs have their channel regions provided in those parts of the well region which have the low surface impurity concentration. The other MOSFETs have their channel regions provided in other parts of the well region.

Abstract: Disclosed herein is a semiconductor device comprising a semiconductor substrate, a well region provided in the surface of the substrate, a plurality of MOSFETs provided in the well region. The well region has parts having a low surface impurity concentration. Some of the MOSFETs have their channel regions provided in those parts of the well region which have the low surface impurity concentration. The other MOSFETs have their channel regions provided in other parts of the well region.

Abstract: In a semiconductor device according to this invention, a first insulating film formed on only a pattern formation conductive film on a semiconductor substrate and having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness of the first insulating film is formed on the semiconductor substrate. A second insulating film having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness and having a refractive index different from that of the first insulating film is formed on only the first insulating film. A total reflectance of the first and second insulating films is less than 25%. A photosensitive film is formed on the second insulating film and exposed through a reticle to form a predetermined pattern. Etching is performed using the photosensitive film having this pattern to form a conductive pattern.

Abstract: Disclosed herein is a semiconductor device comprising a semiconductor substrate, a well region provided in the surface of the substrate, a plurality of MOSFETs provided in the well region. The well region has parts having a low surface impurity concentration. Some of the MOSFETs have their channel regions provided in those parts of the well region which have the low surface impurity concentration. The other MOSFETs have their channel regions provided in other parts of the well region.

Abstract: A transistor element is formed on the surface of a silicon substrate. A tunnel is formed in the silicon substrate at a position right under the transistor element. A contact hole is formed to extend from the surface of the silicon substrate to the contact hole. Silicon oxide films are respectively formed on the inner surfaces of the tunnel and the contact hole. A wiring layer is buried in the tunnel and the contact hole. The wiring layer is connected to a diffusion layer of the transistor element.

Abstract: A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysilicon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

Abstract: In a semiconductor device according to this invention, a first insulating film formed on only a pattern formation conductive film on a semiconductor substrate and having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness of the first insulating film is formed on the semiconductor substrate. A second insulating film having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness and having a refractive index different from that of the first insulating film is formed on only the first insulating film. A total reflectance of the first and second insulating films is less than 25%. A photosensitive film is formed on the second insulating film and exposed through a reticle to form a predetermined pattern. Etching is performed using the photosensitive film having this pattern to form a conductive pattern.

Abstract: A semiconductor device comprises a substrate, first insulation layers formed on the substrate, and a second insulation layer formed on the substrate. The second insulation layer, which acts as a dielectric material of a capacitor component of the semiconductor device, is thinner than each of the first insulation layers.

Abstract: A semiconductor storage device in which plural pairs of cell capacitors arranged in a matrix arrangement on a semiconductor substrate and the plural pairs of cell capacitors are arranged on each row with cell regions placed between the pairs of cell capacitors. This semiconductor storage device is constructed such that a pair of cell capacitors on a given row are connected by a cell plate electrode with other cell capacitors on one diagonal line prolonged from the said pair of cell capacitors but are not connected with the cell capacitors on the other diagonal line.