Abstract: An image processor includes unit pixel circuits, each circuit outputting a pixel value, according to incident light, to an output line; and read circuits in each row and each column, each of which can read out a pixel value of each unit pixel circuit and a result of computing for projection for each row and each column. The unit pixel circuits of each row and column and the corresponding read circuits are connected to each other by discrete output lines. The result of computing for projection readout by the compression processing is an average of pixel values in the unit pixel circuits of each row and of each column.