Abstract: An internal voltage boosting circuit has an oscillator circuit that generates a signal of a prescribed frequency under the control of an oscillator control signal and a stepped-up voltage generating circuit that inputs the signal output by the oscillator circuit and outputs a prescribed stepped-up voltage. In the stepped-up voltage generating circuit, in order to prepare for a next voltage boosting operation, one end of a voltage boosting capacitance is connected to one end of a voltage boosting capacitance of another voltage boosting circuit that operates with a phase difference of 180 degrees, the accumulated charge therein being re-used, after which return is made to the ground potential so as to achieve a voltage boosting to a prescribed stepped-up voltage.

Abstract: A semiconductor memory (100) is disclosed that includes a memory cell array (102) coupled to a register array section (104) that can function as a cache. Access times for misses to the register array section (104) during a continuous read operation can be reduced. A memory cell array (102) is coupled to the register array section (104) by a first transfer bus (TBT1-1 to TBN1-i). First transfer bus (TBT1-1 to TBN1-i) is connected to a local read/write bus (LRWBT and LRWBN) by transistors (106-1 to 108-i) and to register arrays (116-1 to 116-(i+j)) by first switches (118-1 to 118-(i+j)). In a continuous read operation, during a register array section miss, transistors (106-1 to 108-i) are turned on and the first switches (118-1 to 118-(i+j)) are turned on.

Abstract: The present invention provides a semiconductor memory device operable both in a burst mode and in a normal mode, wherein the semiconductor memory device utilizes at least a single normal mode commend both for its original purpose in the normal mode and also for generating, in the burst mode, a burst stop commend to stop a burst mode operation of the semiconductor memory device.

Abstract: According to one embodiment, a semiconductor memory device can include a synchronous dynamic random access memory array and a register array formed from static random access memory cells. The memory device can be used in image processing, and reduce the time for data reads and writes during image reset operations. One embodiment (100) can include a memory cell array (102) having a number of memory cells arranged in rows and columns, and a register array (104) that includes a number of channel registers (106-11 to 106-mn) arranged rows and columns that correspond to at least a portion of the memory cell array rows and columns. The memory cells of a first column and the registers of a corresponding column are connected to one another by data transfer buses (108-1T/108-1N to 108-mT/108-mN). Data values can be written to memory cells and corresponding channel registers (106-11 to 106-mn) at the same time.

Abstract: In a semiconductor device, an input voltage is applied to a gate of a first MIS transistor of a first conductivity type and gates of second and third MIS transistors of a second conductivity type. The first MIS transistor is connected between a first power supply pad and an output node, the second MIS transistor is connected between the output node and a second power supply pad, and the third MIS transistor is connected between the output node and a third power supply pad.