Patents by Inventor Soujanya Narnur

Soujanya Narnur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • QUICK CLEARING OF REGISTERS
    Publication number: 20200371706
    Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Timothy David ANDERSON, Duc Quang BUI, Soujanya NARNUR
  • SYSTEM AND METHOD FOR PREDICATION HANDLING
    Publication number: 20200371711
    Abstract: A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Timothy David ANDERSON, Duc Quang BUI, Joseph ZBICIAK, Sahithi KRISHNA, Soujanya NARNUR, Alan DAVIS
  • Dual register data path architecture with registers in a data file divided into groups and sub-groups
    Patent number: 8880855
    Abstract: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy D Anderson, Duc Quang Bui, Eric Biscondi, Shriram D Moharil, Mujibur Rahman, Soujanya Narnur, Peter Richard Dent, Ashish Rai Shrivastava
  • DUAL REGISTER DATA PATH ARCHITECTURE
    Publication number: 20120079247
    Abstract: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.
    Type: Application
    Filed: September 15, 2011
    Publication date: March 29, 2012
    Inventors: Timothy D. Anderson, Duc Quang Bui, Eric Biscondi, Shriram D. Moharil, Mujibur Rahman, Soujanya Narnur, Peter Richard Dent, Ashish Rai Shrivastava