Abstract: A semiconductor device and a highly reliable circuit are realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.

Abstract: A semiconductor device and a highly reliable circuit are realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.

Abstract: A highly reliable circuit is realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.

Abstract: A highly reliable circuit is realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.

Abstract: An amplifier includes a signal amplification part that outputs an output signal obtained by amplifying an input signal and a common mode voltage VCM of the output signal, and a common mode feedback part that outputs a signal according to a difference between the common mode voltage VCM and a reference potential Vref as a regulation signal SREG. The regulation signal SREG from the common mode feedback part is fed back to a current source of the signal amplification part and a current source of the common mode feedback part.

Abstract: A semiconductor device in which surge breakdown of interlayer-insulating film does not occur even when effectively suppressing variations in etching and proximity effects. The semiconductor comprises dummy patterns 7b that are made from a gate layer and shaped to be disposed within the surface shape of the insulating material of element-isolation areas 3a and are located on the insulating material of the element-isolation areas 3a; wherein dummy patterns 7b are located on an underlayer that includes area directly under wiring layers 10a that are located on layers above the gate layer.

Abstract: A differential signal driver circuit is provided with a driver circuit and a common feedback circuit. The driver circuit is responsive to differential input signals for generating differential output signals from operation currents generated by two current sources. The common feedback circuit controls the current sources to regulate the current levels of the operation currents in response to the differential output signals.

Abstract: An amplifier includes a signal amplification part that outputs an output signal obtained by amplifying an input signal and a common mode voltage VCM of the output signal, and a common mode feedback part that outputs a signal according to a difference between the common mode voltage VCM and a reference potential Vref as a regulation signal SREG. The regulation signal SREG from the common mode feedback part is fed back to a current source of the signal amplification part and a current source of the common mode feedback part.

Abstract: A semiconductor circuit according to an embodiment of the present invention includes a first current mirror operating between a first power supply potential and a second power supply potential, a third power supply potential generated by the first current mirror, a second current mirror operating between the first power supply potential and the second power supply potential, a fourth power supply potential generated by the second current mirror, a circuit operating between the third power supply potential and the fourth power supply potential, and a first conductive type transistor and a second conductive type transistor connected to the circuit in parallel and connected to each other in series.

Abstract: A buffer circuit capable of switching between input mode and output mode includes a first transistor for outputting a prescribed voltage to an input/output terminal depending on a conductive state during the output mode of the buffer circuit, a pre-driver for controlling the conductive state of the first transistor during the output mode of the buffer circuit, and a power supply circuit for providing a first power supply to the pre-driver during the output mode of the buffer circuit and providing or blocking the first power supply to the pre-driver in accordance with an input voltage to the input/output terminal during the input mode of the buffer circuit.

Abstract: A differential signal driver circuit is provided with a driver circuit and a common feedback circuit. The driver circuit is responsive to differential input signals for generating differential output signals from operation currents generated by two current sources. The common feedback circuit controls the current sources to regulate the current levels of the operation currents in response to the differential output signals.

Abstract: A buffer circuit capable of switching between input mode and output mode includes a first transistor for outputting a prescribed voltage to an input/output terminal depending on a conductive state during the output mode of the buffer circuit, a pre-driver for controlling the conductive state of the first transistor during the output mode of the buffer circuit, and a power supply circuit for providing a first power supply to the pre-driver during the output mode of the buffer circuit and providing or blocking the first power supply to the pre-driver in accordance with an input voltage to the input/output terminal during the input mode of the buffer circuit.

Abstract: A semiconductor device in which surge breakdown of interlayer-insulating film does not occur even when effectively suppressing variations in etching and proximity effects. The semiconductor comprises dummy patterns 7b that are made from a gate layer and shaped to be disposed within the surface shape of the insulating material of element-isolation areas 3a and are located on the insulating material of the element-isolation areas 3a; wherein dummy patterns 7b are located on an underlayer that includes area directly under wiring layers 10a that are located on layers above the gate layer.