Abstract: A digital apparatus for controlling an operation of an electric motor capable of realizing a fully digital speed control without creating a severe restriction on data transfer and an excessive demand on the micro-processor. The apparatus includes a micro-processor for carrying out normal speed control processings at normal speed timings; a high speed digital processor for carrying out high speed control processings at high speed timings faster than the normal speed timings; and interface register for interfacing data transmission between the micro-processor and the high speed digital processor; and a timing circuit for receiving access signals from the micro-processor, and producing timing signals based on the high speed timings by using the access signals where the timing signals control timings of the data transmission through the interface register.