Abstract: A memory architecture is provided to enable parallel access along any dimension of an n-dimensional data array. To enable parallel access of s data elements along any dimension, the data elements of n-dimensional data array are mapped to s parallel memory banks in such a way that consecutive s data elements along any dimension are mapped to different memory banks. This mapping is defined by two functions, which define the memory bank number and location within a memory bank for each data element in n-dimensional data array. The necessary and sufficient conditions, which the mapping functions should satisfy in order to enable parallel data access, are described. These generic function pairs are described for all combinations of (n, s). Two particular instances of the mapping, namely circular permutation (rotation) along 0th dimension and dyadic permutation along 0th dimension have been discussed in detail.