Patents by Inventor Soumya S. EACHEMPATI

Soumya S. EACHEMPATI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Link affinitization to reduce transfer latency
    Patent number: 11966330
    Abstract: Examples described herein relate to processor circuitry to issue a cache coherence message to a central processing unit (CPU) cluster by selection of a target cluster and issuance of the request to the target cluster, wherein the target cluster comprises the cluster or the target cluster is directly connected to the cluster. In some examples, the selected target cluster is associated with a minimum number of die boundary traversals. In some examples, the processor circuitry is to read an address range for the cluster to identify the target cluster using a single range check over memory regions including local and remote clusters. In some examples, issuance of the cache coherence message to a cluster is to cause the cache coherence message to traverse one or more die interconnections to reach the target cluster.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: April 23, 2024
    Assignee: Intel Corporation
    Inventors: Vinit Mathew Abraham, Jeffrey D. Chamberlain, Yen-Cheng Liu, Eswaramoorthi Nallusamy, Soumya S. Eachempati
  • LINK AFFINITIZATION TO REDUCE TRANSFER LATENCY
    Publication number: 20200301830
    Abstract: Examples described herein relate to processor circuitry to issue a cache coherence message to a central processing unit (CPU) cluster by selection of a target cluster and issuance of the request to the target cluster, wherein the target cluster comprises the cluster or the target cluster is directly connected to the cluster. In some examples, the selected target cluster is associated with a minimum number of die boundary traversals. In some examples, the processor circuitry is to read an address range for the cluster to identify the target cluster using a single range check over memory regions including local and remote clusters. In some examples, issuance of the cache coherence message to a cluster is to cause the cache coherence message to traverse one or more die interconnections to reach the target cluster.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Vinit MATHEW ABRAHAM, Jeffrey D. CHAMBERLAIN, Yen-Cheng LIU, Eswaramoorthi NALLUSAMY, Soumya S. EACHEMPATI