Abstract: Disclosed are a circuit and a method for adaptively biasing a voltage regulator with minimal output overshoot. The circuit includes an adaptive bias current mirror circuit further including a first transistor and a second transistor, the first transistor and the second transistor having source nodes coupled to a drain node of the first transistor. The circuit includes a common node coupled to the source node of the first transistor and the source node of the second transistor, wherein a source degenerate resistor is coupled to the adaptive bias current mirror circuit and is coupled to the common node and wherein the source degenerate resistor is configured to limit an output peak current of the voltage regulator circuit.

Abstract: The present invention is directed to a trimming circuit and method for replica type voltage regulators. A voltage regulator circuit includes an operational amplifier (OPAMP) and a n-type metal oxide silicon (NMOS) device. An output of the OPAMP is coupled to a gate terminal of the NMOS device. The voltage regulator circuit includes a potential divider circuit comprising a plurality of discrete devices coupled in series. A source terminal of the NMOS device is coupled to the potential divider circuit to form an output feedback node. The body of the NMOS device is biased variably across a plurality of tap points formed between consecutive discrete devices in the potential divider circuit.