Abstract: A driving circuit for a light emitting diode lighting apparatus includes a driving data memory device in which central portion driving data for driving the light emitting diodes are separated into many sections within one cycle of the driving power; a drive controller for reading the central driving data, charging driving data, and outer driving data stored in the driving data memory device; a first D/A converter for converting digital central driving data and outer driving data output from the drive controller to analog signals, and a second D/A converter for converting charging driving data to an analog signal; a static current driving device having static current driving devices respectively connected to tabs of light emitting diodes according to an output signal of the first D/A converter; and a charging static current driving device for charging the charging capacitor according to the output signal from the second D/A converter.

Abstract: The present invention relates to a light-emitting diode (LED) driving circuit for lighting, which divides a specific pattern of driving data for a number of sections within one period or a half period of driving power, stores the divided data in a driving data storage device, and drives LEDs connected in series in an LED array unit using the driving data so as to drive the LEDs with high efficiency, a high power factor, and low total harmonic distortion (HTD).

Abstract: A driving circuit for a light emitting diode lighting apparatus includes a driving data memory device in which central portion driving data for driving the light emitting diodes are separated into many sections within one cycle of the driving power; a drive controller for reading the central driving data, charging driving data, and outer driving data stored in the driving data memory device; a first D/A converter for converting digital central driving data and outer driving data output from the drive controller to analog signals, and a second D/A converter for converting charging driving data to an analog signal; a static current driving device having static current driving devices respectively connected to tabs of light emitting diodes according to an output signal of the first D/A converter; and a charging static current driving device for charging the charging capacitor according to the output signal from the second D/A converter.

Abstract: The present invention relates to a light-emitting diode (LED) driving circuit for lighting, which divides a specific pattern of driving data for a number of sections within one period or a half period of driving power, stores the divided data in a driving data storage device, and drives LEDs connected in series in an LED array unit using the driving data so as to drive the LEDs with high efficiency, a high power factor, and low total harmonic distortion (HTD).

Abstract: An exemplary embodiment of the present invention discloses a light emitting diode (LED) driving device for an LED device having a plurality of LEDs, the driving device including a rectifying unit configured to receive an alternating current (AC) voltage and output a rectified voltage, and a driving control unit configured to drive the plurality of LEDs based on stored data by receiving the rectified voltage at a first period.

Abstract: A cache management system includes a main memory for storing instructions and information for identifying cache control instructions, a central processing unit (CPU) for executing the instructions, an instruction identifier for identifying that an instruction stored the main memory is a cache control instruction, a cache controller for predicting a next instruction to be executed by the CPU and for reading a corresponding program information in advance when the cache control instruction is identified by the instruction identifier, and a cache memory for storing executable instructions and data from the main memory and for supplying the executable instructions to the CPU under the control of the cache controller.

Abstract: An improved parallel multiplier capable of operating an addition operation by connecting a plurality of dividers sequentially, thus providing more simple circuit and reducing operating time thereof, which includes NXM AND-gates each for ANDing each multiplier bit ranging from a least significant bit to a most significant bit with each multiplicand bit in case of multiplying “N” multiplicand bits and “M” multiplier bits and for performing a partial multiplication and for outputting a least significant bit as a result of the multiplication; and a plurality of input-bits dividers, having 2-, 3-, and 4-input-bits dividers, for receiving an output bit of a corresponding location among a rearranged output bit and a quotient bit outputted from a proceeding input bit in case that the output bits of the AND-gates is shifted to the left by a bit in accordance with a conventional binary multiplication method and for outputting a quotient bit and a remaining bit corresponding to each bit of a mult

Abstract: In a register controlling apparatus, whenever a routine is run, a register logicalal address, and the values of a local register pointer and a local register counter are selectively added, and thereby a register physical address and a new value of the local register pointer are outputted, resulting in the setting of the register available domain. Then, when the routine returns to a higher order routine, the set register available domain is released to be called by another subroutine, and further, when a register in another routine is accessed in an arbitrary routine, the register logical address is outputted as the register physical address to achieve the accessing, resulting in accomplishing an enhanced application efficiency of the register and an easy processing of a routine using many registers.

Abstract: A data access circuit for a CPU that individually extracts and processes variable length data or commands from a memory in one clock period provides high speed processing. The circuit includes a program counter for increasing a previous address by a currently decoded command length to compute the next address. The program counter outputs the next address to a data storing unit and a data alignment unit. The data storing unit can include two memories with two decoders and outputs a prescribed length of data corresponding to the next address from the program counter. The data alignment unit aligns the prescribed amount of data output from the data storing unit using the next address. A command decoding unit decodes the aligned data in order to determine a next command and its variable command length, which is used to reset the currently extracted command length used by the program counter. A command execution unit executes the next command received from the command decoding unit.

Abstract: A cache management system includes a main memory for storing instructions and information for identifying cache control instructions, a central processing unit (CPU) for executing the instructions, an instruction identifier for identifying that an instruction stored the main memory is a cache control instruction, a cache controller for predicting a next instruction to be executed by the CPU and for reading a corresponding program information in advance when the cache control instruction is identified by the instruction identifier, and a cache memory for storing executable instructions and data from the main memory and for supplying the executable instructions to the CPU under the control of the cache controller.

Abstract: In a register controlling apparatus, whenever a routine is run, a register logicalal address, and the values of a local register pointer and a local register counter are selectively added, and thereby a register physical address and a new value of the local register pointer are outputted, resulting in the setting of the register available domain. Then, when the routine returns to a higher order routine, the set register available domain is released to be called by another subroutine, and further, when a register in another routine is accessed in an arbitrary routine, the register logical address is outputted as the register physical address to achieve the accessing, resulting in accomplishing an enhanced application efficiency of the register and an easy processing of a routine using many registers.

Abstract: An address alignment system for a semiconductor memory device includes a plurality of address decoders for decoding a received address, dividing m cells of n bit size into at least two blocks, and individually accessing the cells on the block basis; a controlling circuit for producing data input/output selection signals according to the received address; a plurality of cell selectors connected to cells on the same row of the blocks for selecting cells in any one block in response to the data input/output selection signals produced by the controlling circuit; a plurality of input/output selectors for selecting one of the cell selectors to re-align data in the order of addresses according to the data input/output selection signals produced by the controlling circuit; and a plurality of input/output ports each connected to one of the input/output selectors.

Abstract: An improved parallel multiplier capable of operating an addition operation by connecting a plurality of dividers sequentially, thus providing more simple circuit and reducing operating time thereof, which includes NXM AND-gates each for ANDing each multiplier bit ranging from a least significant bit to a most significant bit with each multiplicand bit in case of multiplying "N" multiplicand bits and "M" multiplier bits and for performing a partial multiplication and for outputting a least significant bit as a result of the multiplication; and a plurality of input-bits dividers, having 2-, 3-, and 4-input-bits dividers, for receiving an output bit of a corresponding location among a rearranged output bit and a quotient bit outputted from a proceeding input bit in case that the output bits of the AND-gates is shifted to the left by a bit in accordance with a conventional binary multiplication method and for outputting a quotient bit and a remaining bit corresponding to each bit of a multiplication result.

Abstract: A memory, and associated method of operating the memory, for use with a computer, the memory receiving address information from the computer via an address bus. The memory includes: an odd-address block of memory cells; an even-address block of memory cells; and an enablement circuit for simultaneously enabling either the odd-address block or the even-address block to be read from or written into and enabling a non-data exchange operation, i.e., a memory location access, in the other memory cell block that takes place while the other memory cell block is disabled to read or write.

Abstract: A maximum value selector, for selecting the maximum value among m binary words of n-bits each, including: n unit-bit-parallel comparators connected serially, each comparator comparing bit values at a common position in all the words (the first comparator operating on the most significant, the second comparator operating on the n-1 bit position, . . . and the n-1 comparator operating upon the zeroith bit position) and a set corresponding carry signals bit by bit and outputting the thus-obtained maximum value designating signals to be used as the carry signals of the next lower significant bit; and a multiplexer for outputting the maximum value among m binary words in accordance with the maximum value designating signal output from the unit-bit-parallel comparator associated with the least significant bit.

Abstract: An improved timer oscillation circuit capable of synchronizing an oscillation frequency, which is determined by a time constant of a resistance and a capacitance, to a clock signal, which includes a first voltage comparator, controlled by a clock signal, for charging a first voltage on a second capacitance and for outputting a result obtained by comparing the charged voltage on the second capacitance and a voltage from the first capacitance; and a second voltage comparator, controlled by the clock signal, for charging a voltage outputted from the first capacitance on a third capacitance and for outputting a result by comparing the charged voltage and an electric potential of the second voltage, so that it can be advantageously adopted to a digital circuit by outputting an oscillation signal having a cycle determined by a time constant of a resistance and a capacitance and which is synchronized to a clock signal.

Abstract: A method for coding a semiconductor ROM. The method includes the steps of: carrying out a local oxidizing process on a semiconductor substrate to separate the substrate into field regions and active regions; forming a gate insulating layer; depositing a polysilicon layer; and patterning the structure by applying a photo etching process to form a polysilicon gate only on a portion where an enhancement transistor is to be formed. Further, impurity ions are ion-implanted into a source/drain region by utilizing a gate of an enhancement transistor as a mask, and simultaneously, impurity ions are ion-implanted into a region where a drain, a gate and a source of a depletion transistor are to be formed, whereby n type impurity layers of the same depth are formed to interconnect them.