Patents by Inventor Souta MATSUMOTO

Souta MATSUMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11965582
    Abstract: A worm reducer has: a housing having a wheel housing portion and a worm housing portion; a worm wheel; a worm, a support bearing having an inner ring externally fitted to the tip end portion of the worm and an outer ring; an elastic biasing means elastically biasing the outer ring toward the worm wheel side; and an elastic holding means elastically holding the outer ring from both sides in a direction orthogonal to a biasing direction by the elastic biasing means and to a center axis of the worm housing portion.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: April 23, 2024
    Assignee: NSK LTD.
    Inventors: Ryou Oosawa, Satoshi Ishikuri, Haruhiko Kiyota, Souta Matsumoto, Toru Ishii, Hiroyuki Sugawara
  • Patent number: 11391358
    Abstract: A worm reduction gear, including: an inner diameter side holder in which a bearing is internally fitted and held; an outer diameter side holder which includes a holder holding part in which the inner diameter side holder is internally fitted and held so as to be able to be relatively rotated and moved and to be displaced in a direction orthogonal to a center axis of a worm wheel and a center axis of a worm, and which is internally fitted and held in a holding recessed part of a housing; and an elastic urging member in a circumferential direction which elastically urges the inner diameter side holder against the outer diameter side holder in a direction of rotating in the circumferential direction.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 19, 2022
    Assignee: NSK LTD.
    Inventors: Toru Segawa, Toru Ishii, Souta Matsumoto
  • Publication number: 20220099159
    Abstract: A worm reducer has: a housing having a wheel housing portion and a worm housing portion; a worm wheel; a worm, a support bearing having an inner ring externally fitted to the tip end portion of the worm and an outer ring; an elastic biasing means elastically biasing the outer ring toward the worm wheel side; and an elastic holding means elastically holding the outer ring from both sides in a direction orthogonal to a biasing direction by the elastic biasing means and to a center axis of the worm housing portion.
    Type: Application
    Filed: January 15, 2020
    Publication date: March 31, 2022
    Applicant: NSK Ltd.
    Inventors: Ryou OOSAWA, Satoshi ISHIKURI, Haruhiko KIYOTA, Souta MATSUMOTO, Toru ISHII, Hiroyuki SUGAWARA
  • Publication number: 20190285157
    Abstract: Disclosed herein is a worm reduction gear, including: an inner diameter side holder in which a bearing is internally fitted and held; an outer diameter side holder which includes a holder holding part in which the inner diameter side holder is internally fitted and held so as to be able to be relatively rotated and moved and to be displaced in a direction orthogonal to a center axis of a worm wheel and a center axis of a worm, and which is internally fitted and held in a holding recessed part of a housing; and an elastic urging member in a circumferential direction which elastically urges the inner diameter side holder against the outer diameter side holder in a direction of rotating in the circumferential direction.
    Type: Application
    Filed: July 18, 2017
    Publication date: September 19, 2019
    Applicant: NSK LTD.
    Inventors: Toru SEGAWA, Toru ISHll, Souta MATSUMOTO
  • Patent number: 9991335
    Abstract: Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. The semiconductor device comprises a polarization super junction region and a p-electrode contact region. The polarization super junction region comprises an undoped GaN layer 11, an undoped AlxGa1-xN layer 12 with a thickness not smaller than 25 nm and not larger than 47 nm and 0.17?x?0.35, an undoped GaN layer 13 and a p-type GaN layer 14. When the reduced thickness tR is defined as tR=u+v(1+w×10?18) for the thickness u [nm] of the undoped GaN layer 13, the thickness v [nm] and the Mg concentration w [cm?3] of the p-type GaN layer 14, tR?0.864/(x?0.134)+46.0 [nm] is satisfied.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: June 5, 2018
    Assignee: POWDEC K.K.
    Inventors: Shoko Echigoya, Fumihiko Nakamura, Shuichi Yagi, Souta Matsumoto, Hiroji Kawai
  • Publication number: 20170263710
    Abstract: Provided is a semiconductor element in which a two-dimensional hole gas with an enough concentration can exist, even though the p-type GaN layer is not provided on the topmost surface of the polarization super junction region. The semiconductor element comprises a polarization super junction region comprising an undoped GaN layer 11 with a thickness a [nm] (a is not smaller than 10 nm and not larger than 1000 nm), an AlxGa1-xN layer 12 and an undoped GaN layer 13. The Al composition x and the thickness t [nm] of the AlxGa1-xN layer 12 satisfy the following equation t??(a)x?(a) Where ? is expressed as Log (?)=p0+p1 log (a)+p2{log (a)}2 (p0=7.3295, p1=?3.5599, p2=0.6912) and ? is expressed as ?=p?0+p?1 log (a)+p?2{log (a)}2 (p?0=?3.6509, p?1=1.9445, p?2=?0.3793).
    Type: Application
    Filed: November 5, 2015
    Publication date: September 14, 2017
    Applicant: POWDEC K.K.
    Inventors: Souta MATSUMOTO, Shoko ECHIGOYA, Shuichi YAGI, Fumihiko NAKAMURA, Hiroji KAWAI
  • Publication number: 20160093691
    Abstract: Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. The semiconductor device comprises a polarization super junction region and a p-electrode contact region. The polarization super junction region comprises an undoped GaN layer 11, an undoped AlxGa1-xN layer 12 with a thickness not smaller than 25 nm and not larger than 47 nm and 0.17?x?0.35, an undoped GaN layer 13 and a p-type GaN layer 14. When the reduced thickness tR is defined as tR=u+v(1+w×10?18) for the thickness u [nm] of the undoped GaN layer 13, the thickness v [nm] and the Mg concentration w [cm?3] of the p-type GaN layer 14, tR?0.864/(x?0.134)+46.0 [nm] is satisfied.
    Type: Application
    Filed: November 18, 2014
    Publication date: March 31, 2016
    Inventors: Shoko ECHIGOYA, Fumihiko NAKAMURA, Shuichi YAGI, Souta MATSUMOTO, Hiroji KAWAI