Patents by Inventor Sovan Ghosh
Sovan Ghosh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12334944Abstract: A circuit includes an amplifier, a pre-driver circuit, and an output circuit. The amplifier has a first input, a second input, and an output. The pre-driver circuit has an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier. The output circuit includes a first transistor and a second transistor. The first transistor has a control terminal coupled to the first output of the pre-driver circuit; a first terminal, and a second terminal coupled to the third output of the pre-driver circuit. The second transistor has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference terminal.Type: GrantFiled: December 22, 2023Date of Patent: June 17, 2025Assignee: Texas Instruments IncorporatedInventors: Sovan Ghosh, Visvesvaraya Appala Pentakota
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Patent number: 12273104Abstract: An example apparatus includes a first transistor configured to receive an analog voltage signal; a second transistor configured to receive a first control signal, coupled to the first transistor, and coupled to a first terminal; a third transistor configured to receive a second control signal, receive a supply voltage, and coupled to the first terminal; a capacitor coupled to the first terminal and to ground; a fourth transistor configured to receive a third control signal and coupled to the first terminal; a fifth transistor gate configured to receive a bias voltage, coupled to ground, and coupled to the fourth transistor; a sixth transistor coupled to the fourth transistor and to ground; a seventh transistor configured to receive the supply voltage, coupled to the first terminal and to the sixth transistor; and an eighth transistor coupled to the first terminal, to the sixth transistor, and to ground.Type: GrantFiled: February 28, 2023Date of Patent: April 8, 2025Assignee: Texas Instruments IncorporatedInventors: Sovan Ghosh, Visvesvaraya Appala Pentakota
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Publication number: 20250080096Abstract: An example apparatus includes programmable circuitry configured to: provide a sample signal, a time amplification (TA) signal, and a kick signal to sample and conversion circuitry; sample a differential signal for a first amount of time-based on the sample signal; charge a first capacitor for a second amount of time-based on the first kick signal; after the first amount of time and the second amount of time, charge a second capacitor, the charging based on the first TA signal, the charging to cause a falling edge in a first delay signal; and generating, a rising edge in the delay signal based on the falling edge of O_RST signal.Type: ApplicationFiled: August 31, 2023Publication date: March 6, 2025Inventors: Sovan Ghosh, Visvesvaraya Appala Pentakota
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Publication number: 20250023594Abstract: One example includes an analog-to-digital converter (ADC) front-end system. The system includes a digital step attenuator (DSA) having an input and an output. The system also includes a sampling system having an input coupled to the output of the DSA. The sampling system includes a first sampling capacitor, a second sampling capacitor, and at least one sampling switch. The sampling system can be configured to sample an analog signal current provided from the DSA on the first sampling capacitor and the second sampling capacitor concurrently in response to activation of the at least one sampling switch to integrate the analog signal current as a sampling voltage on both the first and second sampling capacitors. The system further includes an ADC having an input and an output, the input of the ADC coupled to the output of the sampling system.Type: ApplicationFiled: December 27, 2023Publication date: January 16, 2025Inventors: Visvesvaraya A. PENTAKOTA, Sovan GHOSH
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Publication number: 20250007528Abstract: A circuit includes an amplifier, a pre-driver circuit, and an output circuit. The amplifier has a first input, a second input, and an output. The pre-driver circuit has an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier. The output circuit includes a first transistor and a second transistor. The first transistor has a control terminal coupled to the first output of the pre-driver circuit; a first terminal, and a second terminal coupled to the third output of the pre-driver circuit. The second transistor has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference terminal.Type: ApplicationFiled: December 22, 2023Publication date: January 2, 2025Applicant: Texas Instruments IncorporatedInventors: Sovan GHOSH, Visvesvaraya Appala PENTAKOTA
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Publication number: 20240291484Abstract: An example apparatus includes a first transistor configured to receive an analog voltage signal; a second transistor configured to receive a first control signal, coupled to the first transistor, and coupled to a first terminal; a third transistor configured to receive a second control signal, receive a supply voltage, and coupled to the first terminal; a capacitor coupled to the first terminal and to ground; a fourth transistor configured to receive a third control signal and coupled to the first terminal; a fifth transistor gate configured to receive a bias voltage, coupled to ground, and coupled to the fourth transistor; a sixth transistor coupled to the fourth transistor and to ground; a seventh transistor configured to receive the supply voltage, coupled to the first terminal and to the sixth transistor; and an eighth transistor coupled to the first terminal, to the sixth transistor, and to ground.Type: ApplicationFiled: February 28, 2023Publication date: August 29, 2024Inventors: Sovan Ghosh, Visvesvaraya Appala Pentakota
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Patent number: 11527999Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.Type: GrantFiled: September 21, 2020Date of Patent: December 13, 2022Assignee: Texas Instruments IncorporatedInventors: Sovan Ghosh, Amal Kumar Kundu, Laxmi Vivek Tripurari, Anand Subramanian
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Patent number: 11349492Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.Type: GrantFiled: December 4, 2020Date of Patent: May 31, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sovan Ghosh, Minkle Eldho Paul, Laxmi Vivek Tripurari, Amal Kumar Kundu
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Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter
Patent number: 11095300Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.Type: GrantFiled: June 18, 2020Date of Patent: August 17, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sovan Ghosh, Amal Kumar Kundu, Janakiraman Seetharaman -
Publication number: 20210119638Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.Type: ApplicationFiled: December 4, 2020Publication date: April 22, 2021Inventors: Sovan GHOSH, Minkle Eldho PAUL, Laxmi Vivek TRIPURARI, Amal KUMAR KUNDU
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Publication number: 20210006211Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.Type: ApplicationFiled: September 21, 2020Publication date: January 7, 2021Inventors: Sovan GHOSH, Amal KUMAR KUNDU, Laxmi Vivek TRIPURARI, Anand SUBRAMANIAN
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Patent number: 10886933Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.Type: GrantFiled: October 18, 2019Date of Patent: January 5, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sovan Ghosh, Minkle Eldho Paul, Laxmi Vivek Tripurari, Amal Kumar Kundu
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Patent number: 10868558Abstract: An analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (CDAC), a comparator coupled to the CDAC, and a successive approximation register (SAR) control circuit coupled to the CDAC and the comparator. The SAR control circuit is configured to successively select bits of a digital output value. The SAR control circuit is also configured to, after selection of the bits of the digital output value: maintain a state of first switches of the CDAC applied to select a most significant bit of the digital output value, and revert second switches of the CDAC applied to select bits of the digital output value having significance lower than the most significant bit to a state of the second switches prior to selection of the most significant bit.Type: GrantFiled: December 13, 2019Date of Patent: December 15, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Laxmi Vivek Tripurari, Sovan Ghosh, Minkle Eldho Paul
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Patent number: 10826520Abstract: An analog-to-digital converter includes a low voltage power supply rail, a high voltage power supply rail, successive approximation circuit, a level shifter, and a capacitive digital-to-analog converter (CDAC). The successive approximation circuitry is coupled to the low voltage power supply rail. The level shifter is coupled to the high voltage power supply rail and includes inputs coupled to first outputs of the successive approximation circuitry. The CDAC includes a first segment and a second segment. The first segment includes a first plurality of capacitors, and a first plurality of switches coupled to outputs of the level shifter. The second segment includes a second plurality of capacitors, and a second plurality of switches coupled to second outputs of the successive approximation circuitry.Type: GrantFiled: August 9, 2019Date of Patent: November 3, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amal Kumar Kundu, Sovan Ghosh
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Patent number: 10819294Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.Type: GrantFiled: September 18, 2019Date of Patent: October 27, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sovan Ghosh, Amal Kumar Kundu, Laxmi Vivek Tripurari, Anand Subramanian
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Publication number: 20200336118Abstract: A circuit includes first and second gain stages and an output transistor. The second gain stage includes a transconductance amplifier and a variable impedance circuit coupled to an output of the transconductance amplifier. The variable impedance circuit is configured to implement a first impedance level at frequencies below a first frequency threshold and to implement a second impedance level at frequencies above a second frequency level. The first impedance level is larger than the second impedance level. The output transistor has a control input coupled to the variable impedance circuit. At frequencies above the second frequency threshold, the second impedance level is configured to be inversely related to current through the output transistor.Type: ApplicationFiled: September 18, 2019Publication date: October 22, 2020Inventors: Sovan GHOSH, Amal KUMAR KUNDU, Laxmi Vivek TRIPURARI, Anand SUBRAMANIAN
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REDUCED NOISE DYNAMIC COMPARATOR FOR A SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER
Publication number: 20200321970Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.Type: ApplicationFiled: June 18, 2020Publication date: October 8, 2020Inventors: Sovan Ghosh, Amal Kumar Kundu, Janakiraman Seetharaman -
Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter
Patent number: 10727852Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.Type: GrantFiled: August 29, 2019Date of Patent: July 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sovan Ghosh, Amal Kumar Kundu, Janakiraman Seetharaman -
REDUCED NOISE DYNAMIC COMPARATOR FOR A SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER
Publication number: 20190386670Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: Sovan GHOSH, Amal Kumar KUNDU, Janakiraman SEETHARAMAN -
Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter
Patent number: 10447290Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.Type: GrantFiled: December 11, 2017Date of Patent: October 15, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sovan Ghosh, Amal Kumar Kundu, Janakiraman Seetharaman