Abstract: A pulse-width modulation circuit includes an oscillator stage. The oscillator stage includes a first voltage comparator having a first input terminal, a second input terminal and an output terminal. A first capacitor is coupled to the first input terminal of the first voltage comparator. A charging path for the first capacitor is coupled between the first capacitor and the output terminal of the first voltage comparator, the charging path having a first resistance. A discharging path for the first capacitor is coupled between the first capacitor and the output terminal of the first voltage comparator, the discharging path having a second resistance that is different from the first resistance. A duty cycle of a clock signal generated by the oscillator stage is determined based on a first RC time constant for charging the first capacitor and a second RC time constant for discharging the first capacitor.

Abstract: A radiation tolerant discrete reference voltage source includes just two bipolar junction transistors, five resistors, and a Zener diode. Two of the resistors form a voltage divider that outputs a reference voltage. Values of the resistors included in the voltage divider can be selected to output a desired reference voltage level, for example, 5.00V, 4.00V, or 2.50V, which obviates a need to procure unique voltage references for those reference voltage levels and provides design flexibility. The radiation tolerant discrete reference voltage source provides improved control over radiation hardness and does not require high gain transistors. Because relatively few, inexpensive components are used, the radiation tolerant discrete reference voltage source can be produced at a low cost.

Abstract: A radiation tolerant gate driver for power converters with active-clamp reset and active-driven synchronous rectification uses integrated logic drivers for high efficiency and wide input range. A keep alive circuit prevents power train transistors from remaining on for extended durations after a transient or an undervoltage lockout (UVLO) event. Each of the integrated logic drivers includes two gate driver circuits, where one of the gate driver circuits uses the output of the other of the gate driver circuits as input per a logic table of the integrated logic driver, to ensure no shoot-through when the respective power train transistors are turned on and off.

Abstract: A circuit includes a voltage detection path having a first transistor and a second transistor coupled to the first voltage detection path by a first terminal of the second transistor. The first voltage detection path includes: a first current source and a first voltage divider unit coupled to the first current source. The first transistor is coupled to the first voltage divider unit by a first terminal of the first transistor. A first voltage value at a second terminal of the first transistor is configured to switch between a first high voltage value and a first low voltage value at least partially based on a first detection voltage value provided at the first terminal of the first transistor by the first voltage divider unit. A second voltage at a second terminal of the second transistor is configured to switch between a second high voltage value and a second low voltage value at least partially based on the first voltage value at the second terminal of the first transistor.

Abstract: Systems and methods for providing peak current mode control (PCMC) for power converters. Noise immunity is improved by enhancing the signal-to-noise ratio of an inductor (or switch) current to achieve minimum duty cycle resolution and eliminate subharmonic operation that causes high input and output ripples. Current is sensed and translated to a voltage by a current sense resistor for peak current mode control scheme. A direct current (DC) offset voltage is added only during an on-time of the main switch to increase the signal-to-noise ratio. A leading-edge spike caused by turn-on of the main switch is removed by resetting a filter capacitor of a current sense circuit to zero volts after each switching cycle.

Abstract: Systems and methods for providing peak current mode control (PCMC) for power converters. Noise immunity is improved by enhancing the signal-to-noise ratio of an inductor (or switch) current to achieve minimum duty cycle resolution and eliminate subharmonic operation that causes high input and output ripples. Current is sensed and translated to a voltage by a current sense resistor for peak current mode control scheme. A direct current (DC) offset voltage is added only during an on-time of the main switch to increase the signal-to-noise ratio. A leading-edge spike caused by turn-on of the main switch is removed by resetting a filter capacitor of a current sense circuit to zero volts after each switching cycle.

Abstract: Systems and methods for providing peak current mode control (PCMC) for power converters using discrete analog components. A pair of complementary bipolar junction transistors may be used to set a maximum duty cycle for the power converter. PCMC may be achieved using a comparator that compares peak input current to an error feedback signal and terminates a pulse-width modulation (PWM) pulse when the peak input current exceeds the error feedback signal. A magnetic signal transformer may be used to establish a secondary side bias voltage supply, to return the error signal, and to drive an AC-coupled signal for a synchronous gate drive. A synchronous switch may be turned on when the main switch is turned off via an output winding of the flyback transformer and may be turned off by the trailing edge of a clock pulse from the magnetic signal transformer before the main switch is turned on.

Abstract: Systems and methods for providing peak current mode control (PCMC) for power converters using discrete analog components. Peak current mode control functionality for latching, set, reset, clocking and slope compensation is provided via available analog components that provide improved performance, design flexibility, reliability, and radiation tolerance. Discrete analog components may include analog comparators, resistors, capacitors, diodes, etc.

Abstract: A circuit for providing dynamic output current sharing using average current mode control for active-reset and self-driven synchronous rectification with pre-bias startup and redundancy capabilities for power converters. The circuit communicates a secondary side feedback signal to a primary side via a bidirectional magnetic communicator that also provides a secondary voltage supply. Pre-bias startup is achieved by detection of the output current direction and controlling the gate signals of synchronous rectifiers. The circuit permits dynamic current sharing via a single-control signal and automatic master converter selection and promotion.

Abstract: A circuit for providing dynamic output current sharing using average current mode control for active-reset and self-driven synchronous rectification with pre-bias startup and redundancy capabilities for power converters. The circuit communicates a secondary side feedback signal to a primary side via a bidirectional magnetic communicator that also provides a secondary voltage supply. Pre-bias startup is achieved by detection of the output current direction and controlling the gate signals of synchronous rectifiers. The circuit permits dynamic current sharing via a single-control signal and automatic master converter selection and promotion.

Abstract: Systems and methods that provide control circuits having multiple sub-control inputs that control operation of a power electronics device (e.g., a power converter). Each of the multiple sub-control inputs are output from a separate sub-control circuit that includes a feedback circuit having an input tied to a common control node. The common control node is coupled to an input of a controller (e.g., a PWM controller). Outputs of each of the sub-control circuits are coupled to the common control node by a respective switch (e.g., diode, transistor, etc.) so that each of the sub-control circuits may be selectively coupled to the common control node to provide a control signal to a controller. Since components of each of the feedback compensations circuits are biased at a regulation voltage instead of a higher power supply voltage, the control circuit may switch between control modes with minimal delay.

Abstract: A circuit for providing dynamic output current sharing using average current mode control for active-reset and self-driven synchronous rectification with pre-bias startup and redundancy capabilities for power converters. The circuit communicates a secondary side feedback signal to a primary side via a bidirectional magnetic communicator that also provides a secondary voltage supply. Pre-bias startup is achieved by detection of the output current direction and controlling the gate signals of synchronous rectifiers. The circuit permits dynamic current sharing via a single-control signal and automatic master converter selection and promotion.

Abstract: Systems and methods are disclosed for providing over-voltage protection for power converters. An over-voltage protection loop includes an error amplifier that maintains an external reference voltage within a highly precise range that can be used to provide a highly precise output voltage from the over-voltage protection loop. The over-voltage protection loop may also include feedback impedance that delays the output of the over-voltage protection loop. The delay may prevent the over-voltage protection loop from being engaged due to voltage transients output from a main servo loop circuit that provides a nominal output voltage under normal operation, thus allowing the threshold voltage and output voltage of the over-voltage protection loop to be set close to the nominal output voltage of the main servo loop circuit.

Abstract: Systems and methods are disclosed for providing over-voltage protection for power converters. An over-voltage protection loop includes an error amplifier that maintains an external reference voltage within a highly precise range that can be used to provide a highly precise output voltage from the over-voltage protection loop. The over-voltage protection loop may also include feedback impedance that delays the output of the over-voltage protection loop. The delay may prevent the over-voltage protection loop from being engaged due to voltage transients output from a main servo loop circuit that provides a nominal output voltage under normal operation, thus allowing the threshold voltage and output voltage of the over-voltage protection loop to be set close to the nominal output voltage of the main servo loop circuit.

Abstract: Systems and methods that provide control circuits having multiple sub-control inputs that control operation of a power electronics device (e.g., a power converter). Each of the multiple sub-control inputs are output from a separate sub-control circuit that includes a feedback circuit having an input tied to a common control node. The common control node is coupled to an input of a controller (e.g., a PWM controller). Outputs of each of the sub-control circuits are coupled to the common control node by a respective switch (e.g., diode, transistor, etc.) so that each of the sub-control circuits may be selectively coupled to the common control node to provide a control signal to a controller. Since components of each of the feedback compensations circuits are biased at a regulation voltage instead of a higher power supply voltage, the control circuit may switch between control modes with minimal delay.

Abstract: Systems and methods for providing a self-driven synchronous rectification circuit for an active-clamp forward converter which includes automatically enhancing synchronous MOSFETs and maximizing input voltage range. The gate signals for the synchronous MOSFETs are derived from a unipolar magnetic coupling signal instead of a bipolarized magnetic coupling signal. The unipolar signal is retained for fully enhanced driving of the MOSFETs at low line voltage and the unipolar signal is automatically converted to a bipolar signal at high line amplitude due to line variance to maximize input voltage range by utilizing non-polarized characteristics of the MOSFET gate-to-source voltage (Vgs). The circuit permits efficient scaling for higher output voltages such as 12 volts DC or 15 volts DC, without requiring extra windings on the transformer of the forward converter.

Abstract: Systems and methods that provide control circuits having multiple sub-control inputs that control operation of a power electronics device (e.g., a power converter). Each of the multiple sub-control inputs are output from a separate sub-control circuit that includes a feedback circuit having an input tied to a common control node. The common control node is coupled to an input of a controller (e.g., a PWM controller). Outputs of each of the sub-control circuits are coupled to the common control node by a respective switch (e.g., diode, transistor, etc.) so that each of the sub-control circuits may be selectively coupled to the common control node to provide a control signal to a controller. Since components of each of the feedback compensations circuits are biased at a regulation voltage instead of a higher power supply voltage, the control circuit may switch between control modes with minimal delay.