Abstract: According to one embodiment, a multiple signal detect circuit (100) can include a detect node (102) and a reference node (104). The potential of the detect node (102) can be discharged (or charged) at a rate that depends upon the number of active input signals (M1 to Mn). The potential of the reference node (104) can be discharged (or charged) at a reference rate. The reference rate can be greater than the rate at which the detect node (102) is discharged (or charged) when one input signal is activated, and less than the rate at which the detect node (102) is discharged (or charged) when two input signals are activated. A differential voltage between the detect node (102) and reference node (104) can be amplified by an amplifier (110).

Abstract: An analog to digital converter circuit includes encoder circuitry which employs a dummy bit line to derive timing signals employed in establishing stable, valid output digital signal information. For almost all binary codes of interest, the dummy bit line employed may actually comprise a portion of an otherwise unused bit line. The present invention is also distinguished in that it employs a clocked regenerative bit line sustainer circuit driven by dummy bit line derived timing signals. Additionally, the present invention also preferably employs a folded antiparallel architecture in which the bit lines are disposed in a generally U-shaped surrounding the parallel segments along their outer edges.