Patents by Inventor Sowmiya Jayachandran

Sowmiya Jayachandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200034061
    Abstract: A multilevel memory subsystem includes a persistent memory device that can access data chunks sequentially or randomly to improve read latency, or can prefetch data blocks to improve read bandwidth. A media controller dynamically switches between a first read mode of accessing data chunks sequentially or randomly and a second read mode of prefetching data blocks. The media controller switches between the first and second read modes based on a number of read commands pending in a command queue.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 30, 2020
    Inventors: Sahar KHALILI, Zvika GREENFIELD, Sowmiya JAYACHANDRAN, Robert J. ROYER, JR., Dimpesh PATEL
  • Publication number: 20200019227
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Rajesh Sundaram, William Low, Sowmiya Jayachandran
  • Patent number: 10437307
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification. The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh Sundaram, William Low, Sowmiya Jayachandran
  • Publication number: 20190278503
    Abstract: A method is described. The method includes performing write operations on a plurality of NVRAM semiconductor chips of a memory module while tracking power budget headroom for performing the write operations and while monitoring current draw on a supply voltage rail that is coupled to the plurality of NVRAM semiconductor chips. The method further includes detecting the current draw has reached a threshold. The method further includes ceasing or diminishing the write operations in response to the detecting.
    Type: Application
    Filed: May 29, 2019
    Publication date: September 12, 2019
    Inventors: Sowmiya JAYACHANDRAN, Andrew MORNING-SMITH, Brian R. MCFARLANE, William T. GLENNAN, Emily P. CHUNG
  • Patent number: 10153015
    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran
  • Patent number: 9916104
    Abstract: Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: March 13, 2018
    Assignee: Intel Corporation
    Inventors: Sowmiya Jayachandran, Rajesh Sundaram, Robert Faber
  • Publication number: 20180068695
    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 8, 2018
    Inventors: Prashant S. DAMLE, Frank T. HADY, Paul D. RUBY, Kiran PANGAL, Sowmiya JAYACHANDRAN
  • Publication number: 20170364135
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification. The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.
    Type: Application
    Filed: August 31, 2017
    Publication date: December 21, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Rajesh Sundaram, William Low, Sowmiya Jayachandran
  • Patent number: 9818458
    Abstract: Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Sowmiya Jayachandran, Rajesh Sundaram, Robert Faber
  • Patent number: 9792963
    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: October 17, 2017
    Assignee: Intel Corporation
    Inventors: Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran
  • Patent number: 9778723
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: October 3, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh Sundaram, William Low, Sowmiya Jayachandran
  • Publication number: 20170185136
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Rajesh Sundaram, William Low, Sowmiya Jayachandran
  • Publication number: 20170115916
    Abstract: Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.
    Type: Application
    Filed: November 7, 2016
    Publication date: April 27, 2017
    Applicant: Intel Corporation
    Inventors: Sowmiya Jayachandran, Rajesh Sundaram, Robert Faber
  • Patent number: 9417684
    Abstract: A mechanism is described for facilitating power governance of non-volatile memory devices using a power governing mechanism employed at a computing device according to one embodiment of the invention. A method of embodiments of the invention includes maintaining a credit pool having a plurality of credits to be released to a plurality of memory channels associated with a plurality of non-volatile memory devices. The plurality of credits may be used to provide sufficient power to perform memory operations associated with a computing device. The method may further include receiving a credit request having a petition to obtain one or more credits for a memory channel of the plurality of memory channels to facilitate performance of a memory operation, determining whether the one or more credits are available in the credit pool, and retrieving the one or more credits from the credit pool, if the one or more credits are available in the credit pool.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Simon D. Ramage, Jason A. Gayman, Joerg Hartung, Curtis A. Gittens, Sowmiya Jayachandran, Richard P. Mangold
  • Publication number: 20160189757
    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
    Type: Application
    Filed: November 11, 2015
    Publication date: June 30, 2016
    Inventors: PRASHANT S. DAMLE, FRANK T. HADY, PAUL D. RUBY, KIRAN PANGAL, SOWMIYA JAYACHANDRAN
  • Patent number: 9202547
    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Prashant S. Damle, Frank T. Hady, Paul D. Ruby, Kiran Pangal, Sowmiya Jayachandran
  • Publication number: 20140281203
    Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: PRASHANT S. DAMLE, FRANK T. HADY, PAUL D. RUBY, KIRAN PANGAL, SOWMIYA JAYACHANDRAN
  • Patent number: 8001444
    Abstract: A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: August 16, 2011
    Assignee: Intel Corporation
    Inventors: Andrew Vogan, Jawad B. Khan, Sowmiya Jayachandran
  • Publication number: 20090172213
    Abstract: In some embodiments, after a hold off time following issuance of a memory command has elapsed, a status read operation is performed to determine a status of the memory command. In some embodiments, if the memory command has not yet completed, a polling interval is used to perform a status read operation to determine the status of the memory command after the polling interval has expired, and repeating the process until the memory command has been completed. Other embodiments are described and claimed.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Sowmiya Jayachandran, Jawad B. Khan, Randall K. Webb, Robert W. Faber
  • Publication number: 20090044078
    Abstract: A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 12, 2009
    Inventors: Andrew Vogan, Jawad B. Khan, Sowmiya Jayachandran