Patents by Inventor So Yeon MOON
So Yeon MOON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128423Abstract: A display apparatus can include a flexible substrate including a penetrating hole, a first thin film transistor including a first semiconductor layer, a second thin film transistor including a second semiconductor layer, and a first planarization layer on the first and second thin film transistors. The display apparatus can include a connection electrode on the first planarization layer electrically connected to the first or second thin film transistor, a second planarization layer on the first planarization layer, a first electrode on the second planarization layer electrically connected to the connection electrode, and a bank layer on the second planarization layer exposing a portion of the first electrode. The display apparatus includes a light-emitting layer on the portion of the first electrode exposed by the bank layer, the light-emitting layer including an emission material layer between first and second organic layers, and a second electrode on the light-emitting layer.Type: ApplicationFiled: December 22, 2023Publication date: April 18, 2024Applicant: LG Display Co., Ltd.Inventors: So-Young NOH, So-Yeon JE, Ki-Tae KIM, Kyeong-Ju MOON, Hyuk JI
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Patent number: 11557534Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and a first encapsulant covering at least a portion of each of the inactive surface and a side surface of the semiconductor chip. A metal layer is disposed on the first encapsulant, and includes a first conductive layer and a second conductive layer, sequentially stacked. A connection structure is disposed on the active surface of the semiconductor chip, and includes a first redistribution layer electrically connected to the connection pad. A lower surface of the first conductive layer is in contact with the first encapsulant and has first surface roughness, and an upper surface of the first conductive layer is in contact with the second conductive layer and has second surface roughness smaller than the first surface roughness.Type: GrantFiled: July 30, 2021Date of Patent: January 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: So Yeon Moon, Ji Hye Shim, Seung Hun Chae
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Publication number: 20210358838Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and a first encapsulant covering at least a portion of each of the inactive surface and a side surface of the semiconductor chip. A metal layer is disposed on the first encapsulant, and includes a first conductive layer and a second conductive layer, sequentially stacked. A connection structure is disposed on the active surface of the semiconductor chip, and includes a first redistribution layer electrically connected to the connection pad. A lower surface of the first conductive layer is in contact with the first encapsulant and has first surface roughness, and an upper surface of the first conductive layer is in contact with the second conductive layer and has second surface roughness smaller than the first surface roughness.Type: ApplicationFiled: July 30, 2021Publication date: November 18, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: So Yeon MOON, Ji Hye SHIM, Seung Hun CHAE
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Patent number: 11107762Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and a first encapsulant covering at least a portion of each of the inactive surface and a side surface of the semiconductor chip. A metal layer is disposed on the first encapsulant, and includes a first conductive layer and a second conductive layer, sequentially stacked. A connection structure is disposed on the active surface of the semiconductor chip, and includes a first redistribution layer electrically connected to the connection pad. A lower surface of the first conductive layer is in contact with the first encapsulant and has first surface roughness, and an upper surface of the first conductive layer is in contact with the second conductive layer and has second surface roughness smaller than the first surface roughness.Type: GrantFiled: October 24, 2019Date of Patent: August 31, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: So Yeon Moon, Ji Hye Shim, Seung Hun Chae
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Publication number: 20200135633Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and a first encapsulant covering at least a portion of each of the inactive surface and a side surface of the semiconductor chip. A metal layer is disposed on the first encapsulant, and includes a first conductive layer and a second conductive layer, sequentially stacked. A connection structure is disposed on the active surface of the semiconductor chip, and includes a first redistribution layer electrically connected to the connection pad. A lower surface of the first conductive layer is in contact with the first encapsulant and has first surface roughness, and an upper surface of the first conductive layer is in contact with the second conductive layer and has second surface roughness smaller than the first surface roughness.Type: ApplicationFiled: October 24, 2019Publication date: April 30, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: So Yeon MOON, Ji Hye SHIM, Seung Hun CHAE
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Publication number: 20200135631Abstract: A semiconductor package includes a semiconductor chip having a connection pad; an encapsulant covering at least a portion of the semiconductor chip; and an interconnect structure disposed on the semiconductor chip and the encapsulant. The interconnect structure includes a first insulating layer, a first redistribution layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, the first redistribution layer is electrically connected to the connection pad, and when a thickness of the first redistribution layer is a, and a gap between patterns of the first redistribution layer is b, b/a is 4 or less.Type: ApplicationFiled: October 23, 2019Publication date: April 30, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Kwan SEO, Seung Hun CHAE, So Yeon MOON
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Publication number: 20200118985Abstract: A semiconductor package includes a semiconductor, a passive component disposed in parallel with the semiconductor chip and having a connection electrode, and a connection structure on a lower surface of the passive component. The connection structure includes a first metal layer electrically connected to the connection electrode, a second metal layer on the same level as the first metal layer and disposed adjacent to the first metal layer, and a wiring insulating layer having an insulating region filling the first and second metal layers and extending in one direction. A minimum width of the insulating region is referred to as a first width, and a shortest distance between one end of the passive component and one end of the insulating region on the same level is referred to as a spacing distance, and the spacing distance may be twice or more than the first width.Type: ApplicationFiled: August 19, 2019Publication date: April 16, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Hun CHAE, Young Kwan Seo, So Yeon Moon, Jung Hyun Lee, Hye Yeong Jo
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Publication number: 20190229047Abstract: A fan-out semiconductor package includes: a semiconductor chip; a passive element disposed side by side with the semiconductor chip in a horizontal direction; a redistribution member electrically connected to the semiconductor chip and the passive element and disposed beneath the semiconductor chip and the passive element; and an encapsulant encapsulating the semiconductor chip and the passive element, wherein the redistribution member includes passive element connection vias having a rectangular transverse cross section for the purpose of electrical connection to the passive element.Type: ApplicationFiled: September 17, 2018Publication date: July 25, 2019Inventors: So Yeon MOON, Gun LEE, Jun Hyeong PARK