Abstract: The present invention relates to a novel squaramide derivative and a use thereof and provides a novel derivative through the strategy of replacing a compound having a urea core with the bioisolate squaramide, whereby the derivative exhibits an anticancer activity through eIF2? phosphorylation efficacy, wherein squaramide has a characteristic structure retaining a double bond linked to the carbonyl groups and the squaramide structure can be prepared by mediating a precursor bearing an amine group to the squarate ring, which is a squaric ring, through a conjugate addition reaction.

Abstract: The present invention relates to a novel squaramide derivative and a use thereof and provides a novel derivative through the strategy of replacing a compound having a urea core with the bioisolate squaramide, whereby the derivative exhibits an anticancer activity through eIF2? phosphorylation efficacy, wherein squaramide has a characteristic structure retaining a double bond linked to the carbonyl groups and the squaramide structure can be prepared by mediating a precursor bearing an amine group to the squarate ring, which is a squaric ring, through a conjugate addition reaction.

Abstract: A semiconductor device includes a substrate; an active region including a first impurity region and a second impurity region spaced apart from the first impurity region; an isolation region defining the active region; a gate structure intersecting the active region and extending in a first direction parallel to the substrate; a first pad pattern disposed on the first impurity region; a second pad pattern disposed on the second impurity region; a bit line disposed on the first pad pattern and extending in a second direction, wherein the second direction is perpendicular to the first direction and parallel to the substrate; and a contact structure on the second pad pattern, wherein the second pad pattern has a first side surface and a second side surface opposing each other in the first direction that are both curved along a plane parallel to the substrate.

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.

Abstract: A semiconductor device for evaluating characteristics of a transistor is provided. The semiconductor device includes a substrate, an active area defined on the substrate, an insulated gate configured to be formed on the active area, a first source layer and a first drain layer configured to be formed on the active area in a first two-way direction of the gate, and a second source layer and a second drain layer configured to be formed on the active area in a second two-way direction of the gate. The first source layer, the first drain layer, and the second drain layer are formed as a first conductive type. The second source layer is formed as a second conductive type.

Abstract: A semiconductor device for evaluating characteristics of a transistor is provided. The semiconductor device includes a substrate, an active area defined on the substrate, an insulated gate configured to be formed on the active area, a first source layer and a first drain layer configured to be formed on the active area in a first two-way direction of the gate, and a second source layer and a second drain layer configured to be formed on the active area in a second two-way direction of the gate. The first source layer, the first drain layer, and the second drain layer are formed as a first conductive type. The second source layer is formed as a second conductive type.