Patents by Inventor So-Yeong SHIN

So-Yeong SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit and memory
    Patent number: 11423963
    Abstract: An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: August 23, 2022
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Deog-Kyoon Jeong, Han-Gon Ko, Chan-Ho Kye, So-Yeong Shin
  • INTEGRATED CIRCUIT AND MEMORY
    Publication number: 20200211605
    Abstract: An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator.
    Type: Application
    Filed: November 18, 2019
    Publication date: July 2, 2020
    Inventors: Deog-Kyoon JEONG, Han-Gon KO, Chan-Ho KYE, So-Yeong SHIN