Abstract: The present invention relates to an anthracene derivative compound having a characteristic structure in which an aliphatic aromatic mixed ring group is substituted, and to an organic light-emitting device comprising same. The present invention relates to a high-efficiency and long-lifespan organic light-emitting device having remarkably improved luminous efficiency and lifespan characteristics by adopting the anthracene derivative compound according to the present invention as a host of a light-emitting layer, and adopting a polycyclic compound having a characteristic structure as a dopant of the light-emitting layer.

Abstract: The present invention relates to a novel organic light emitting device comprising two light emitting layers, and more specifically, to a novel organic light emitting device in which at least two light emitting layers are included, wherein by using a compound having a specific structure as a host material in at least one light emitting layer, the organic light emitting device is capable of realizing device characteristics such as high luminous efficiency, long lifespan, and low voltage driving.

Abstract: A semiconductor memory device includes an additive latency setting unit configured to receive a mode setting code from an external unit in response to the mode setting signal during a mode setting operation, set an additive latency value in response to the mode setting code, and receive the mode setting code in response to the additive latency setting signal during a normal operation, and an additive latency changing unit configured to change the additive latency value in response to the mode setting code during the normal operation.

Abstract: A semiconductor memory device includes an additive latency setting unit configured to receive a mode setting code from an external unit in response to the mode setting signal during a mode setting operation, set an additive latency value in response to the mode setting code, and receive the mode setting code in response to the additive latency setting signal during a normal operation, and an additive latency changing unit configured to change the additive latency value in response to the mode setting code during the normal operation.