Patents by Inventor Spandana V. Rachamalla

Spandana V. Rachamalla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210209277
    Abstract: Method, apparatus and computer program product for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities comprising extracting design heterogeneity extremities from an RTL design; accounting for the design heterogeneity extremities during macro clock and data signals activity abstraction to generate improved macro activity abstractions; accounting for the design heterogeneity extremities during macro clock and data switching capacitance abstraction to generate improved macro capacitance abstractions; and using improved macro activity abstractions and improved macro capacitance abstractions during hierarchical chip power analysis.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 8, 2021
    Inventors: ARUN JOSEPH, SPANDANA V. RACHAMALLA, RAHUL RAO, SHASHIDHAR REDDY
  • Patent number: 11036905
    Abstract: Method, apparatus and computer program product for hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities comprising extracting design heterogeneity extremities from an RTL design; accounting for the design heterogeneity extremities during macro clock and data signals activity abstraction to generate improved macro activity abstractions; accounting for the design heterogeneity extremities during macro clock and data switching capacitance abstraction to generate improved macro capacitance abstractions; and using improved macro activity abstractions and improved macro capacitance abstractions during hierarchical chip power analysis.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: June 15, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arun Joseph, Spandana V. Rachamalla, Rahul Rao, Shashidhar Reddy
  • Patent number: 10884055
    Abstract: A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Anand Haridass, Arun Joseph, Charles R. Lefurgy, Spandana V. Rachamalla
  • Patent number: 10572614
    Abstract: Aspects of the present invention include a method, system and computer program product that provides for improved localized self-heating analysis during IC design. The method includes a processor for modeling a power characteristic and a thermal resistance characteristic for each one of a plurality of locations within a cell that is being designed into an integrated circuit; for performing a self-heating analysis to determine an amount of heat at each one of the plurality of locations within the cell; and for creating a thermal profile for the cell, wherein the thermal profile includes a maximum self-heating value for each of the plurality of locations within the cell and includes an average self-heating value for the cell, and wherein the maximum self-heating value and the average self-heating value are derived from the determined amount of heat at each one of the plurality of locations within the cell.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nagashyamala R. Dhanwada, Arun Joseph, Arya Madhusoodanan, Spandana V. Rachamalla
  • Patent number: 10204198
    Abstract: Aspects of the present invention include a method, system and computer program product that provides for improved localized self-heating analysis during IC design. The method includes a processor for modeling a power characteristic and a thermal resistance characteristic for each one of a plurality of locations within a cell that is being designed into an integrated circuit; for performing a self-heating analysis to determine an amount of heat at each one of the plurality of locations within the cell; and for creating a thermal profile for the cell, wherein the thermal profile includes a maximum self-heating value for each of the plurality of locations within the cell and includes an average self-heating value for the cell, and wherein the maximum self-heating value and the average self-heating value are derived from the determined amount of heat at each one of the plurality of locations within the cell.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: February 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nagashyamala R. Dhanwada, Arun Joseph, Arya Madhusoodanan, Spandana V. Rachamalla
  • Publication number: 20180372797
    Abstract: A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.
    Type: Application
    Filed: May 25, 2018
    Publication date: December 27, 2018
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Anand Haridass, Arun Joseph, Charles R. Lefurgy, Spandana V. Rachamalla
  • Publication number: 20180210992
    Abstract: Aspects of the present invention include a method, system and computer program product that provides for improved localized self-heating analysis during IC design. The method includes a processor for modeling a power characteristic and a thermal resistance characteristic for each one of a plurality of locations within a cell that is being designed into an integrated circuit; for performing a self-heating analysis to determine an amount of heat at each one of the plurality of locations within the cell; and for creating a thermal profile for the cell, wherein the thermal profile includes a maximum self-heating value for each of the plurality of locations within the cell and includes an average self-heating value for the cell, and wherein the maximum self-heating value and the average self-heating value are derived from the determined amount of heat at each one of the plurality of locations within the cell.
    Type: Application
    Filed: October 25, 2017
    Publication date: July 26, 2018
    Inventors: Nagashyamala R. Dhanwada, Arun Joseph, Arya Madhusoodanan, Spandana V. Rachamalla
  • Publication number: 20180210989
    Abstract: Aspects of the present invention include a method, system and computer program product that provides for improved localized self-heating analysis during IC design. The method includes a processor for modeling a power characteristic and a thermal resistance characteristic for each one of a plurality of locations within a cell that is being designed into an integrated circuit; for performing a self-heating analysis to determine an amount of heat at each one of the plurality of locations within the cell; and for creating a thermal profile for the cell, wherein the thermal profile includes a maximum self-heating value for each of the plurality of locations within the cell and includes an average self-heating value for the cell, and wherein the maximum self-heating value and the average self-heating value are derived from the determined amount of heat at each one of the plurality of locations within the cell.
    Type: Application
    Filed: January 20, 2017
    Publication date: July 26, 2018
    Inventors: Nagashyamala R. Dhanwada, Arun Joseph, Arya Madhusoodanan, Spandana V. Rachamalla
  • Patent number: 10031180
    Abstract: A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Anand Haridass, Arun Joseph, Charles R. Lefurgy, Spandana V. Rachamalla
  • Publication number: 20170023639
    Abstract: A system for post-silicon leakage characterization is configured to apply a rail voltage to a hardware component; cause the hardware component to operate at a particular frequency; cause a cooling device, coupled to the hardware component, to operate at a cooling capacity; run a workload on the hardware component after applying the rail voltage, causing the hardware component to operate at a particular frequency, and causing the cooling device to operate at a particular cooling capacity; discontinue the workload and clocks of the hardware component after a temperature of the hardware component has reached a steady high point; continuously measure temperature and leakage power of the hardware component after discontinuing the workload until the temperature of the hardware component has reached a steady low point; and adjust a power management procedure for the hardware component based on measured temperature and measured leakage power of the hardware component.
    Type: Application
    Filed: July 22, 2015
    Publication date: January 26, 2017
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Anand Haridass, Arun Joseph, Charles R. Lefurgy, Spandana V. Rachamalla