Patents by Inventor Sparsh SINGHAI

Sparsh SINGHAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240370369
    Abstract: Reconfigurable shared memory systems, and related processor-based systems and methods are disclosed. The reconfigurable shared memory system can be included in a processor-based system to provide memory for data storage. In exemplary aspects, the reconfigurable shared memory system not only includes the dedicated memory and the general memory (e.g., system cache memory), but also includes a reconfigurable memory. The reconfigurable memory can be configured as either part of addressable memory space of the dedicated memory if an application requires such additional dedicated memory, and/or configured as part of the addressable memory space of the general memory to provide additional memory to other clients for increased processing performance if such reconfigurable memory is not needed as part of the dedicated memory. The dedicated memory does not have to be sized to the worst-case size requirements of a given application.
    Type: Application
    Filed: October 11, 2023
    Publication date: November 7, 2024
    Inventors: George Patsilaras, Sparsh Singhai, Subbarao Palacharla, Simon Peter William Booth, Girish Bhat, Ling Feng Huang, Scott Cheng, Yen-Kuan Wu, Mohammad Tamjidi
  • Patent number: 11803472
    Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: October 31, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Girish Bhat, Subbarao Palacharla, Jeffrey Shabel, Isaac Berk, Kedar Bhole, Vipul Gandhi, George Patsilaras, Sparsh Singhai
  • Publication number: 20230029696
    Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Inventors: Girish Bhat, Subbarao Palacharla, Jeffrey Shabel, Isaac Berk, Kedar Bhole, Vipul Gandhi, George Patsilaras, Sparsh Singhai
  • Patent number: 11520706
    Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: December 6, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Alain Artieri, Rakesh Kumar Gupta, Subbarao Palacharla, Kedar Bhole, Laurent Rene Moll, Carlo Spitale, Sparsh Singhai, Shyamkumar Thoziyoor, Gopi Tummala, Christophe Avoinne, Samir Ginde, Syed Minhaj Hassan, Jean-Jacques Lecler, Luigi Vinci
  • Publication number: 20220350749
    Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Inventors: Alain ARTIERI, Rakesh Kumar GUPTA, Subbarao PALACHARLA, Kedar BHOLE, Laurent Rene MOLL, Carlo SPITALE, Sparsh SINGHAI, Shyamkumar THOZIYOOR, Gopi TUMMALA, Christophe AVOINNE, Samir GINDE, Syed Minhaj HASSAN, Jean-Jacques LECLER, Luigi VINCI