Abstract: This patent application describes (a) software to help people design monitoring systems and (b) methods to facilitate enhanced data flow management (including from large numbers of simultaneous sources), diagnostic and statistical analyses based on novel concepts of data compression using statistical state space techniques. The design assistance is structured around known but not widely practiced procedures such as documented in Graves, Rens and Rutz (2011). For data flow management, the present invention may transmit and store an estimated state space model only when the last stored model is not adequate to predict recent observations. It may also transmit and store outliers and samples of regular observations. This unique data storage format requires new methods for data analysis to properly extract the information contained therein.

Abstract: In one embodiment, wafers are processed to build test structures in the wafers. The wafers may be processed in tools of process steps belonging to a process module. The test structures may be tested to obtain defectivity data. Tool process parameters may be monitored and collected as process tool data. Other information about the wafers, such as metrology data and product layout attribute, may also be collected. A model describing the relationship between the defectivity data and process tool data may be created and thereafter used to relate the process tool data to a yield of the process module. The model may initially be an initial model using process tool data from a limited number of test wafers that contain test structures. The model may also be an expanded model using process tool data from product wafers containing embedded test structures in areas with no product devices.

Abstract: An integrated circuit (IC) device fabrication process may be monitored by processing product wafers to fabricate product IC devices, collecting process tool data from tools used to fabricate the product IC devices, and testing the product IC devices. To predict and monitor yield, the process tool data collected during processing and the defectivity data from testing the product IC devices may be input to a yield model that also takes into account design information particular to the product devices. The design information may comprise layout attributes of the product devices. The yield model may be generated from a defectivity model created by processing test wafers to fabricate test structures, collecting process tool data from tools used to fabricate the test structures, and testing the test structures. The test structures may have varying layout attributes to cover a design space allowed by design rules for particular product IC devices.