Abstract: A color space converter (100) is disclosed. The color space converter includes an input data MUX (110), a first and second look-up table (LUT) (104 and 106), an arithmetic logic unit (ALU) (108), and an output MUX (112). In a standard indexed color look-up mode, indexed pixel data are coupled to the LUTs (104 and 106) each of which provides direct color data to the output MUX (112). Depending upon a control signal, the output MUX (112) couples one of the direct color lines to an output. In a color conversion mode, the LUTs (104 and 106) store conversion constants. Input pixel data of a first color space format is coupled to the LUTs (104 and 106) and the ALU (108). The resulting conversion constants output from the LUTs (104 and 106) are added with portions of the input pixel data in the ALU (108) to generate direct color data of a second color space format.

Abstract: In one embodiment, a computer graphics system (100) stores pixel data in a combined look-up table value/lighting modulation value format (RLUT8L4) in a display back buffer (110). Data in the back buffer (110) are transferred to a front buffer (112) by a look-up and modify bit block transfer operation (LMBLT) (118). The LMBLT (118) looks up the look-up table value portion (RLUT8) of the pixel data in a render look-up table (RLUT) (116) to generate fully-lit color components of the pixel (CR, CG, CB). The color components are multiplied by the lighting value (L4) to generate a lighting modified pixel (RGB).According to another embodiment, pixel data are stored in the back buffer (110) and a front buffer (206) in the combined format (RLUT8L4). The buffers (110 and 206) are swapped according to conventional double buffering techniques. Pixel data are used to generate analog display device control signals by a look-up and modify digital-to-analog converter (LMDAC) (312).

Abstract: A Blt accelerator method and apparatus (10) are disclosed. A sequencing engine (18) generates appropriate source and destination addresses in response to values stored in host addressable registers (16). Data are read into a storage unit (22) in an initial Blt operation. In subsequent Blt operations data are read from a source data location in combination with the data from the storage unit (22) into an arithmetic logic unit (ALU) (20). The ALU (20) performs a selected arithmetic/logic operation on the input data and stores the result back in the storage unit (22). In this manner, consecutive, subsequent, chained Blt operations may accumulate data. Shift circuits (34) and saturation add capabilities of the ALU (20) are further provided along with methods for the acceleration of pixel filtering, interpolation, and blending, as well as motion compensation in MPEG decoding.

Abstract: A memory addressing method and system is disclosed. In a preferred embodiment, a 48-bit wide memory array is provided wherein eight, 32-bit groups of data are addressable at six (6) memory address locations. Six of the eight 32-bit data groups are addressable at the six memory address locations, while the remaining two 32-bit groups are addressable at aligned, memory address pairs. No page break will occur across the memory address pairs. The contents of the memory are accessed through linear and contiguous addressing. No divide by three operation is required.

Abstract: A method and apparatus of displaying video and graphics data together in a computer graphics display using only the memory needed for the graphics display includes determining the location of the video window in the frame buffer, writing video data to the portion of the frame buffer bounded by the video window. During the raster scan of the frame buffer, if the raster position is within the video window, video data are read from the video data addresses within the video window. When the displayed video window position is changed, the video data are moved accordingly.

Abstract: A display refresh system (10) is disclosed wherein a display image is stored in a screen memory (12) as a number of screen rows (26) having consecutive addressable units. A redundancy memory (38) includes a redundancy row (48) corresponding to each screen row (26). Each redundancy row (48) stores run length data that indicates the number of identical consecutive addressable units within a screen row (26). Addressable units are written with accompanying run lengths to a FIFO (54). A register repeater (56) repeats the addressable unit at the FIFO output (62) a number of times equal to the run length. The run length is used to advance the refresh address to the next group of identical consecutive addressable units within the screen row (26).

Abstract: A display control circuit controls the outputs of the three video DACs of an RGB monitor on a window-to-window basis to enable the display of motion video and text on the same screen with different brightness and/or tint. A digital overdrive signal, synchronized to the video DAC digital inputs, is used to enable added DAC elements for the pixels in the video windows only. Stored digital instructions determine how many and which added DAC elements are enabled by the overdrive bit(s). By storing different instructions for each of the three video DACs, the circuit may also provide window-dependent tint control. By increasing the number of bits of digital data synchronized to the digital DAC inputs, the stored instructions may be reduced or eliminated. In this case, each of several windows may be set to differing brightness and tint levels.