Abstract: This application discloses a computing system to identify a stage of a logic pipeline described in a circuit design that, when implemented in configurable hardware, spans between partitions in the configurable hardware. The computing system can modify the circuit design to alter a timing for logic operations in the logic pipeline, which reduces slack in at least one stage in the logic pipeline adjacent to the identified stage in the logic pipeline. The computing system can utilize the slack reduced from at least one of the stages adjacent to the identified stage to increase a clock frequency in the configurable hardware or increase a time available for propagation delay associated with the identified stage. The computing system can generate a configuration for the configurable hardware that implements the logic pipeline with the altered timing in the configurable hardware.

Abstract: This application discloses an device disposed on a substrate, and a heat sink disposed on the substrate over the device. The heat sink disposed on the substrate forms a cavity to hold a fluid between the heat sink and the device. The fluid can absorb heat emitted by the device and transfer at least a portion of the absorbed heat to the heat sink. A gasket can be disposed between and in contact with the substrate and the heat sink. The gasket can prevent the fluid from exiting the cavity formed by the heat sink disposed on the substrate. The heat sink can have an opening to the cavity, which can be detachably sealed by a plug. The plug can reduce a pressure within the cavity or allow removal of gas bubbles in the fluid held in the cavity.

Abstract: This application discloses an device disposed on a substrate, and a heat sink disposed on the substrate over the device. The heat sink disposed on the substrate forms a cavity to hold a fluid between the heat sink and the device. The fluid can absorb heat emitted by the device and transfer at least a portion of the absorbed heat to the heat sink. A gasket can be disposed between and in contact with the substrate and the heat sink. The gasket can prevent the fluid from exiting the cavity formed by the heat sink disposed on the substrate. The heat sink can have an opening to the cavity, which can be detachably sealed by a plug. The plug can reduce a pressure within the cavity or allow removal of gas bubbles in the fluid held in the cavity.

Abstract: This application discloses a device that emits heat during operation, and an enclosure having walls forming a cavity to hold a first fluid. The walls also form a recess to retain a second fluid external from the cavity. The device can be disposed in the recess and at least partially submerged in the second fluid. The second fluid can absorb the heat emitted by the device and transfer the absorbed heat to the first fluid through the walls of the enclosure shared between the cavity and the recess. The enclosure can include an inlet port configured to allow the first fluid into the cavity and an outlet port configured to output the first fluid from the cavity. A flow of the first fluid through the cavity from the inlet port to the outlet port can dissipate the heat transferred from the device to the first fluid.

Abstract: This application discloses a computing system to identify a stage of a logic pipeline described in a circuit design that, when implemented in configurable hardware, spans between partitions in the configurable hardware. The computing system can modify the circuit design to alter a timing for logic operations in the logic pipeline, which reduces slack in at least one stage in the logic pipeline adjacent to the identified stage in the logic pipeline. The computing system can utilize the slack reduced from at least one of the stages adjacent to the identified stage to increase a clock frequency in the configurable hardware or increase a time available for propagation delay associated with the identified stage. The computing system can generate a configuration for the configurable hardware that implements the logic pipeline with the altered timing in the configurable hardware.

Abstract: This application discloses performing functional verification on a circuit design describing an electronic device and a computing system to determine occurrences of coverpoints and coverage crosses within a covergroup based on the results of the functional verification of the circuit design. Each coverpoint corresponds to a signal state or a variable value in the circuit design during the functional verification. Each of the coverage crosses corresponds to a different plurality of the coverpoints occurring concurrently. The computing system can generate a graphical presentation of the covergroup. The graphical presentation include nodes, each of which corresponding to the coverpoints or the coverage crosses. The nodes can be arranged in the graphical presentation based on connectivity between the coverpoints and the coverage crosses and clustered in the graphical presentation based on the occurrences of the coverpoints and coverage crosses during the functional verification of the circuit design.

Abstract: A barrier for use in a barrier system is described. The barrier is movable to control access past the barrier, and said barrier comprises a media support means arranged to support a removable media to be displayed. The support means defines a media receiving path along which the media is movable to an inserted position in which the media is displayed.

Abstract: An integrated circuit and method of operating the integrated circuit to access external memory are provided. The integrated circuit comprises interconnect logic for coupling master logic units and slave logic units to enable transactions to be performed, each transaction comprising an address transfer from a master logic unit to a slave logic unit and one or more data transfers between that master logic unit and that slave logic unit. At least one master logic unit is operable when seeking to access data from an external memory to initiate a transaction by issuing the address transfer via the interconnect logic, the transaction having format information associated therewith used to format the one or more data transfers of the transaction for transfer over the interconnect logic. A memory controller acts as a slave logic unit for the transaction, and is coupled to the external memory via an external bus.