Abstract: Methods, apparatuses, and systems that allow a microprocessor to optimally select an assist unit (co-processor) to reduce completion times for completing processing requests to execute functions. The methods, apparatuses, and systems include assist unit hardware, assist unit management software, or a combination of the two to optimally select the assist unit for completing a specific processing request. In optimally selecting an assist unit, the methods, apparatuses, and systems calculate estimated times for completing the processing request with conventional means and with assist units. The times are then compared to determine the fastest time for completing a specific processing request.

Abstract: Methods are disclosed of compiling a software application having multiple functions. At least one of the functions is identified as a targeted function having a significant contribution to performance of the software application. A code version of the targeted function is generated with one of multiple machine models corresponding to different target utilizations for a target architecture, specifically corresponding to the one with the greatest of the different target utilizations. The generated code version of the targeted function is matched with an application thread of the target architecture.

Abstract: Embodiments of the invention provide systems and methods for automatically and adaptively optimizing compilation of application code using a rule-based optimization analyzer (RUBOA) that can command a compiler to apply and adapt optimizations at the code segment level according to gathered performance data. For example, source code can be canonically compiled, and annotations can associate compiled code sections with source code sections. The generated binary can then be executed and monitored to gather performance characteristics. The RUBOA can apply the gathered performance characteristics and annotations to a pre-defined rule set to generate compiler optimizations, each associated with and parametrically tailored to respective source code segments.

Abstract: A compilation method is provided for automated user error correction. The method includes using a compiler driver run by a processor to receive a source file for compilation. With a compiler component invoked by the compiler driver, the method includes identifying an error in the source file such as a linking problem or syntax error in the user's program. The method includes receiving with the compiler driver an error message corresponding to the identified error. With an error corrector module run by the processor, the method includes processing the error message to determine an error correction for the identified error in the source file. The compiler driver modifies the source file based on the error correction and compiles the modified source file with the compiler component.

Abstract: A compilation method is provided for correcting compiler errors that include compiler internal errors and errors produced by running a validation suite. The method includes running a compiler on a computer and storing a set of optimization levels in memory accessible by the compiler. The method includes receiving a source file with the compiler that includes a user-defined optimization level to be used in compiling the source file. The method includes identifying a set of functions within the source file and using compiler components to compile these functions using the original optimization level. When the compiling results in an internal error occurring and being reported for one or more of the functions, the method includes using an optimization adjustment module to process the internal error and assign an adjusted or lower optimization level to the one or more functions and recompiling of these functions again with the lower optimization level.

Abstract: Embodiments include systems and methods for generating an application code binary that exploits new platform-specific capabilities, while maintaining backward compatibility with other older platforms. For example, application code is profiled to determine which code regions are main contributors to the runtime execution of the application. For each hot code region, a determination is made as to whether multiple versions of the hot code region should be produced for different target platform models. Each hot code region can be analyzed to determine if benefits can be achieved by exploiting platform-specific capabilities corresponding to each of N platform models, which can result in between one and N versions of that particular hot code region. Navigation instructions are generated as part of the application code binary to permit a target machine to select appropriate versions of the hot code sections at load time, according to the target machine's capabilities.

Abstract: A system and method for minimizing register spills during compilation. A compiler reallocates spilled variables from stack memory to other available registers. Although a corresponding register file may not have available registers for storage, the compiler identifies available registers in other locations for storage. The compiler identifies available registers in an alternate register file, wherein the alternate register file may be a floating-point register file which is then used for spilled integer variables. Other instruction type combinations between spilled variables and alternate register files are possible. When an available register within the alternate register file is identified, the compiler modifies the program instructions to allocate the corresponding spilled variable to the available register.

Abstract: Embodiments include systems and methods for reducing instruction cache miss penalties during application execution. Application code is profiled to determine “hot” code regions likely to experience instruction cache miss penalties. The application code can be linearized into a set of traces that include the hot code regions. Embodiments traverse the traces in reverse, keeping track of instruction scheduling information, to determine where an accumulated instruction latency covered by the code blocks exceeds an amount of latency that can be covered by prefetching. Each time the accumulated latency exceeds the amount of latency that can be covered by prefetching, a prefetch instruction can be scheduled in the application code. Some embodiments insert additional prefetches, merge prefetches, and/or adjust placement of prefetches to account for scenarios, such as loops, merging or forking branches, edge confidence values, etc.

Abstract: Methods are disclosed of compiling a software application having multiple functions. At least one of the functions is identified as a targeted function having a significant contribution to performance of the software application. A code version of the targeted function is generated with one of multiple machine models corresponding to different target utilizations for a target architecture, specifically corresponding to the one with the greatest of the different target utilizations. The generated code version of the targeted function is matched with an application thread of the target architecture.

Abstract: Embodiments of the invention provide systems and methods for throughput-aware software pipelining in compilers to produce optimal code for single-thread and multi-thread execution on multi-threaded systems. A loop is identified within source code as a candidate for software pipelining. An attempt is made to generate pipelined code (e.g., generate an instruction schedule and a set of register assignments) for the loop in satisfaction of throughput-aware pipelining criteria, like maximum register count, minimum trip count, target core pipeline resource utilization, maximum code size, etc. If the attempt fails to generate code in satisfaction of the criteria, embodiments adjust one or more settings (e.g., by reducing scalarity or latency settings being used to generate the instruction schedule).

Abstract: A system and method for speculatively parallelizing non-countable loops in a multi-threaded application. A multi-core processor receives instructions for a multi-threaded application. The application may contain non-countable loops. Non-countable loops have an iteration count value that cannot be determined prior to the execution of the non-countable loop, a loop index value that cannot be non-speculatively determined prior to the execution of an iteration of the non-countable loop, and control that is not transferred out of the loop body by a code line in the loop body. The compiler replaces the non-countable loop with a parallelized loop pattern that uses outlined function calls defined in a parallelization library (PL) in order to speculatively execute iterations of the parallelized loop. The parallelized loop pattern is configured to squash and re-execute any speculative thread of the parallelized loop pattern that is signaled to have a transaction failure.

Abstract: Embodiments of the invention provide systems and methods for automatically parallelizing loops with non-speculative pipelined execution of chunks of iterations with pre-computation of selected values. Non-DOALL loops are identified and divided the loops into chunks. The chunks are assigned to separate logical threads, which may be further assigned to hardware threads. As a thread performs its runtime computations, subsequent threads attempt to pre-compute their respective chunks of the loop. These pre-computations may result in a set of assumed initial values and pre-computed final variable values associated with each chunk. As subsequent pre-computed chunks are reached at runtime, those assumed initial values can be verified to determine whether to proceed with runtime computation of the chunk or to avoid runtime execution and instead use the pre-computed final variable values.

Abstract: A compilation method and mechanism for parallelizing program code. A method for compilation includes analyzing source code and identifying candidate code for parallelization. Having identified one or more suitable candidates, the profitability of parallelizing the candidate code is determined. If the profitability determination meets a predetermined criteria, then the candidate code may be parallelized. If, however, the profitability determination does not meet the predetermined criteria, then the candidate code may not be parallelized. Candidate code may comprises a loop, and determining profitability of parallelization may include computing a probability of transaction failure for the loop. Additionally, a determination of an execution time of a parallelized version of the loop is made. If the determined execution time is less than an execution time of a non-parallelized version of said loop by at least a given amount, then the loop may be parallelized.

Abstract: A system and method for automatic efficient parallelization of code combined with hardware transactional memory support. A software application may contain a transaction synchronization region (TSR) utilizing lock and unlock transaction synchronization function calls for a shared region of memory within a shared memory. The TSR is replaced with two portions of code. The first portion comprises hardware transactional memory primitives in place of lock and unlock function calls. Also, the first portion ensures no other transaction is accessing the shared region without disabling existing hardware transactional memory support. The second portion performs a fail routine, which utilizes lock and unlock transaction synchronization primitives in response to an indication that a failure occurs within said first portion.

Abstract: Methods are disclosed of compiling a software application having multiple functions. At least one of the functions is identified as a targeted function having a significant contribution to performance of the software application. A code version of the targeted function is generated with one of multiple machine models corresponding to different target utilizations for a target architecture, specifically corresponding to the one with the greatest of the different target utilizations. The generated code version of the targeted function is matched with an application thread of the target architecture.

Abstract: A method and mechanism for using threads in a computing system. A multithreaded computing system is configured to execute a first thread and a second thread. Responsive to the first thread detecting a launch point for a function, the first thread is configured to provide an indication to the second thread that the second thread may begin execution of a given function. The launch point of the function precedes an actual call point of the function in an execution sequence. The second thread is configured to initiate execution of the function in response to the indication. The function includes one or more inputs and the second thread uses anticipated values for each of the one or more inputs. When the first thread reaches a call point for the function, the first thread is configured to use a results of the second thread's execution, in response to determining the anticipated values used by the second thread were correct.

Abstract: A system and method for automatically parallelizing a computer program for multi-threaded execution. A compiler identifies and parallelizes non-DOALL parallel regions, such as loops, within a computer program. The compiler determines enhanced helper thread instructions based upon the main body instructions of the non-DOALL region. These helper thread instructions are inserted ahead of the main body instructions within each of the plurality of threads, rather than within a single main thread. Next, synchronization instructions are inserted in one or more threads such that the main body of work of each thread is performed in a pipelined manner. The helper thread instructions within each thread may reduce the total execution time of each thread.

Abstract: A system and method for automatically controlling run-time parallelization of a software application. A buffer is allocated during execution of program code of an application. When a point in program code near a parallelized region is reached, demand information is stored in the buffer in response to reaching a predetermined first checkpoint. Subsequently, the demand information is read from the buffer in response to reaching a predetermined second checkpoint. Allocation information corresponding to the read demand information is computed and stored the in the buffer for the application to later access. The allocation information is read from the buffer in response to reaching a predetermined third checkpoint, and the parallelized region of code is executed in a manner corresponding to the allocation information.

Abstract: A method for compiling application source code that includes selecting multiple loops for parallelization. The multiple loops include a first loop and a second loop. The method further includes partitioning the first loop into a first set of chunks, partitioning the second loop into a second set of chunks, and calculating data dependencies between the first set of chunks and the second set of chunks. A first chunk of the second set of chunks is dependent on a first chunk of the first set of chunks. The method further includes inserting, into the first loop and prior to completing compilation, a precedent synchronization instruction for execution when execution of the first chunk of the first set of chunks completes, and completing the compilation of the application source code to create an application compiled code.

Abstract: Embodiments of the invention provide systems and methods for throughput-aware software pipelining in compilers to produce optimal code for single-thread and multi-thread execution on multi-threaded systems. A loop is identified within source code as a candidate for software pipelining. An attempt is made to generate pipelined code (e.g., generate an instruction schedule and a set of register assignments) for the loop in satisfaction of throughput-aware pipelining criteria, like maximum register count, minimum trip count, target core pipeline resource utilization, maximum code size, etc. If the attempt fails to generate code in satisfaction of the criteria, embodiments adjust one or more settings (e.g., by reducing scalarity or latency settings being used to generate the instruction schedule).