Abstract: The present invention is related to an image sensor comprising an array of rows (i) and columns (j) of pixels (Xij), all the pixels of one column of the array being connected to at least one common pixel output line (Ij) having at least one memory element (Mj) and at least a first amplifying element (Aj), all these amplifying elements (Aj) being connected to a common output amplifier (D). According to one preferred embodiment, said image sensor comprises: a second amplifying element (Bj) on the output of the memory element (Mj); said common output amplifier (D) having at least two input terminals; means (S1) for switching the pixel's signal on the common output line (Ij) and the memory element's signal (Mj) to respectively third and second amplifying element (Aj and Bj) of one column; and means (S2) for switching the two output signals of the amplifying elements (Aj, Bj) of one column to respectively first and second input terminals of said common output amplifier (D).

Abstract: A method for calibrating a low pass filter is disclosed. The low pass filter comprises a plurality of transconductor cells. The method comprises generating a test signal to the low pass filter and suppressing even-order harmonics due to transistor mismatches within the plurality of transconductor cells. By adding a small number of transistors, the mismatch-induced even order harmonics can be greatly reduced. Even-order harmonics are minimized through the application of a control voltage. A method for calibrating against transistor mismatch utilizing a CMOS transconductor that is based on the regulated cascode topology is disclosed. The method is designed to provide suppression of the even-order harmonics, a very small increase in power and a silicon area of the transconductor cell. A well-defined offset is provided by biasing one of the mismatched transistors.