Abstract: An apparatus has processing circuitry to perform data processing in response to instructions; at least one control storage element to store internal state for controlling operation of the processing circuitry; and checksum generating circuitry to generate a checksum based on at least one item of internal state stored in the at least one control storage element. The checksum is stored in a diagnostic storage location from which information is accessible to a diagnostic control agent (e.g. software executing on the processing circuitry and/or an external device). This makes design of software test libraries for detecting hardware faults much more efficient.

Abstract: A simulation of software test program executing upon a primary model of a portion of a data processing apparatus is performed to identify uncovered (undetected) failures. A formal method analysis is then performed upon a combination of the primary model and a fault-simulating model simulating the uncovered failures in order to identify software stimuli that can render the uncovered failures detectable. The identified software stimuli are then added to the software test program to increase the failure coverage. The process is performed iteratively until a desired level of failure coverage is achieved.

Abstract: An apparatus has processing circuitry to perform data processing in response to instructions; at least one control storage element to store internal state for controlling operation of the processing circuitry; and checksum generating circuitry to generate a checksum based on at least one item of internal state stored in the at least one control storage element. The checksum is stored in a diagnostic storage location from which information is accessible to a diagnostic control agent (e.g. software executing on the processing circuitry and/or an external device). This makes design of software test libraries for detecting hardware faults much more efficient.

Abstract: In a processing pipeline, hazards involving conditional instructions may be ignored when the conditional instruction would fail its test condition and there are no earlier instructions than the conditional instruction remaining which could potentially update the condition status information used to evaluate the test condition.

Abstract: A simulation of software test program executing upon a primary model of a portion of a data processing apparatus is performed to identify uncovered (undetected) failures. A formal method analysis is then performed upon a combination of the primary model and a fault-simulating model simulating the uncovered failures in order to identify software stimuli that can render the uncovered failures detectable. The identified software stimuli are then added to the software test program to increase the failure coverage. The process is performed iteratively until a desired level of failure coverage is achieved.

Abstract: In a pipeline where first and second instruction slots process first and second instructions in parallel and a duplicated processing resource is provided at both first and second pipeline stages, a second instruction in the second instruction slot requiring the duplicated processing resource is controlled to use the duplicated processing resource at the first pipeline stage when a first number of cycles by which the instruction in the first instruction slot is to be stalled is greater than or equal to a second number of cycles by which the second instruction would be stalled to allow its operand to be available in time for the first pipeline stage.

Abstract: In a processing pipeline, hazards involving conditional instructions may be ignored when the conditional instruction would fail its test condition and there are no earlier instructions than the conditional instruction remaining which could potentially update the condition status information used to evaluate the test condition.

Abstract: In a pipeline where first and second instruction slots process first and second instructions in parallel and a duplicated processing resource is provided at both first and second pipeline stages, a second instruction in the second instruction slot requiring the duplicated processing resource is controlled to use the duplicated processing resource at the first pipeline stage when a first number of cycles by which the instruction in the first instruction slot is to be stalled is greater than or equal to a second number of cycles by which the second instruction would be stalled to allow its operand to be available in time for the first pipeline stage.