Patents by Inventor Spyros Panaoussis

Spyros Panaoussis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6404356
    Abstract: A method and apparatus are provided for compressing data. The method includes the steps of determining a flux, scaling factor and sign of a difference between a new sample and a previous sample and encoding the difference of the new sample over the previous sample based upon the determined flux, scaling factor and sign of the new sample.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: June 11, 2002
    Assignee: Cennoid Technologies, Inc.
    Inventor: Spyros Panaoussis
  • Patent number: 5949355
    Abstract: The present invention relates to data compression systems and methods wherein text can be compressed by encoding repetitions of blocks of characters, or through a straight encoding scheme that converts eight-bit character values to four-bit character values by eliminating values for characters that are not valid word-starting characters or valid next-letter characters for a given preceding letter. Block compression is accomplished through the use of data structures that track the successive occurrence of valid block-repetition starting characters, and their lengths. Repeat-relative block compression is accomplished by detecting character sequences that can be expressed as the value of a previously-occurring character sequence plus or minus an offset.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: September 7, 1999
    Assignee: Cennoid Technologies, Inc.
    Inventor: Spyros Panaoussis
  • Patent number: 5896100
    Abstract: An analog-to-digital converter circuit is disclosed that is capable of converting both positive and negative analog input signals, and that is capable of operating as either an analog-to-digital converter or a digital-to-analog converter. The converter includes a modifying filter, a series of substantially identical converter stages, and a restoring filter. An original reference signal is provided, coupled to a resistor array to provide a stage reference signal to each converter stage that is equivalent to the value of the bit of an N-bit binary word corresponding to that stage. An incoming analog signal is modified to ensure that it is positive before applying it in parallel to the converter stages. Each converter stage compares the modified analog signal to the sum of its own reference signal and the value of all stage reference signals for prior converter stages where the digital output of the stage was a binary "1.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: April 20, 1999
    Assignee: Cennoid Technologies, Inc.
    Inventor: Spyros Panaoussis
  • Patent number: 5684478
    Abstract: The present invention relates to data compression systems and methods wherein text can be compressed by encoding repetitions of blocks of characters, or through a straight encoding scheme that converts eight-bit character values to four-bit character values by eliminating values for characters that are not valid word-starting characters or valid next-letter characters for a given preceding letter. Block compression is accomplished through the use of data structures that track the successive occurrence of valid block-repetition starting characters, and their lengths. Repeat-relative block compression is accomplished by detecting character sequences that can be expressed as the value of a previously-occurring character sequence plus or minus an offset.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: November 4, 1997
    Assignee: Cennoid Technologies, Inc.
    Inventor: Spyros Panaoussis
  • Patent number: 5594438
    Abstract: An analog-to-digital converter circuit is disclosed that is capable of converting both positive and negative analog input signals, and that is capable of operating as either an analog-to-digital converter or a digital-to-analog converter. The converter includes a modifying filter, a series of substantially identical converter stages, and a restoring filter. An original reference signal is provided, coupled to a resistor array to provide a stage reference signal to each converter stage that is equivalent to the value of the bit of an N-bit binary word corresponding to that stage. An incoming analog signal is modified to ensure that it is positive before applying it in parallel to the converter stages. Each converter stage compares the modified analog signal to the sum of its own reference signal and the value of all stage reference signals for prior converter stages where the digital output of the stage was a binary "1.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: January 14, 1997
    Assignee: Cennoid Technologies Inc.
    Inventor: Spyros Panaoussis
  • Patent number: 4586091
    Abstract: A method and system for high density data recording is provided. Parallel encoded digital data are converted to corresponding serial format data words. Individual cycles of a periodic signal are selectively attenuated in accordance with the logic state of individual bits of the serial data words. By determining the relative level of the periodic signal during periods defined by individual cycles of the signal, the sequence of logic data bits forming the serial data words can be reconstructed.
    Type: Grant
    Filed: May 3, 1984
    Date of Patent: April 29, 1986
    Assignee: Kalhas Oracle, Inc.
    Inventor: Spyro Panaoussis