Patents by Inventor Spyros Tragoudas

Spyros Tragoudas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10312888
    Abstract: Various embodiments of a robust double node upset tolerant latch in which all internal and external nodes are capable of recovering the previous value after a single event upset are disclosed.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 4, 2019
    Assignee: Board of Trustees of Southern Illinois University on Behalf of Southern Illinois University Carbondale
    Inventors: Adam Watkins, Spyros Tragoudas
  • Patent number: 10240910
    Abstract: Systems and methods for compressive image sensor techniques based on sparse measurement matrices are disclosed. A method to perform compressive sensing (CS) measurement operations for image sensors limits pixel summation to be within neighboring pixels and hence dramatically simplifies CS image sensor circuits and reduces their power consumption while providing better image quality compared to conventional random measurement matrix based methods. A sparse measurement matrix is applied to pixel data to generate a desired number of summation groups, each summation group consisting of outputs from an equal number of pixel cells. Each pair of summation groups contains the same number of shared outputs from pixel cells. From the summation groups, an image captured by the pixel cells is recovered.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: March 26, 2019
    Assignee: Board of Trustees of Southern Illinois University on Behalf of Southern Illinois University Carbondale
    Inventors: Stefan Leitner, Haibo Wang, Spyros Tragoudas
  • Publication number: 20180367124
    Abstract: Various embodiments of a robust double node upset tolerant latch in which all internal and external nodes are capable of recovering the previous value after a single event upset are disclosed.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 20, 2018
    Inventors: Adam Watkins, Spyros Tragoudas
  • Patent number: 10084435
    Abstract: Disclosed are a latch circuit and method for preventing double node upsets (DNUs). A first, second, and third storage circuit, each comprising four inputs and an output, are electrically interconnected with a first and second three-input c-element circuit, each comprising three inputs and an output, and a two-input c-element circuit comprising two inputs and an output. The output of the first storage circuit is connected to a first input of the first three-input c-element circuit, a first input of the third storage circuit and a third input of the second storage circuit. The output of the second storage circuit is connected to a second input of the first three-input c-element circuit, a first input of the two-input c-element circuit, and a second input of the second three-input c-element circuit.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 25, 2018
    Assignee: Board of Trustees of Southern Illinois University on Behalf of Southern Illinois University Carbondale
    Inventors: Adam Watkins, Spyros Tragoudas
  • Publication number: 20180073860
    Abstract: Systems and methods for compressive image sensor techniques based on sparse measurement matrices are disclosed. A method to perform compressive sensing (CS) measurement operations for image sensors limits pixel summation to be within neighboring pixels and hence dramatically simplifies CS image sensor circuits and reduces their power consumption while providing better image quality compared to conventional random measurement matrix based methods. A sparse measurement matrix is applied to pixel data to generate a desired number of summation groups, each summation group consisting of outputs from an equal number of pixel cells. Each pair of summation groups contains the same number of shared outputs from pixel cells. From the summation groups, an image captured by the pixel cells is recovered.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 15, 2018
    Applicant: Board of Trustees of Southern Illiniois University on Behalf of Southern Illinois University Carbond
    Inventors: Stefan Leitner, Haibo Wang, Spyros Tragoudas
  • Publication number: 20180076797
    Abstract: Disclosed are a latch circuit and method for preventing double node upsets (DNUs). A first, second, and third storage circuit, each comprising four inputs and an output, are electrically interconnected with a first and second three-input c-element circuit, each comprising three inputs and an output, and a two-input c-element circuit comprising two inputs and an output. The output of the first storage circuit is connected to a first input of the first three-input c-element circuit, a first input of the third storage circuit and a third input of the second storage circuit. The output of the second storage circuit is connected to a second input of the first three-input c-element circuit, a first input of the two-input c-element circuit, and a second input of the second three-input c-element circuit.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 15, 2018
    Applicant: Board of Trustees of Southern Illinois University on Behalf of Southern Illinois University Carbonda
    Inventors: Adam Watkins, Spyros Tragoudas