Abstract: An apparatus sets an operating voltage of a shared power rail in a multi-core electronic device. The apparatus includes a system-on-chip (SoC) having multiple cores with each core in the SoC configured to report an operating status. The apparatus includes an operating state aggregator configured to receive the operating status reported from each core in the SoC and to select the selected operating voltage based on the operating status from each core. A voltage regulator is in communication with the operating state aggregator and a power management integrated circuit (PMIC). The selected operating voltage is then programmed into the (PMIC) to control the shared power rail.

Abstract: An apparatus sets an operating voltage of a shared power rail in a multi-core electronic device. The apparatus includes a system-on-chip (SoC) having multiple cores with each core in the SoC configured to report an operating status. The apparatus includes an operating state aggregator configured to receive the operating status reported from each core in the SoC and to select the selected operating voltage based on the operating status from each core. A voltage regulator is in communication with the operating state aggregator and a power management integrated circuit (PMIC). The selected operating voltage is then programmed into the (PMIC) to control the shared power rail.

Abstract: Methods, systems, and devices for refreshing a display of a device are described. A device may identify a type of content to be displayed. For example, the type of content may be associated with a given application. The device may determine, based at least in part on the type of content, a periodicity for a histogram analysis operation for the display. The device may then perform the histogram analysis operation according to the periodicity. For example, the device may compare a histogram for a frame of the content to a scene change threshold according to the periodicity. The device may determine one or more pixel adjustment parameters for the display based at least in part on the histogram analysis operation. The device may display one or more frames on the display based at least in part on the one or more pixel adjustment parameters.

Abstract: Methods, systems, and devices for refreshing a display of a device are described. A device may identify a type of content to be displayed. For example, the type of content may be associated with a given application. The device may determine, based at least in part on the type of content, a periodicity for a histogram analysis operation for the display. The device may then perform the histogram analysis operation according to the periodicity. For example, the device may compare a histogram for a frame of the content to a scene change threshold according to the periodicity. The device may determine one or more pixel adjustment parameters for the display based at least in part on the histogram analysis operation. The device may display one or more frames on the display based at least in part on the one or more pixel adjustment parameters.

Abstract: Systems, methods, and apparatus are herein disclosed for performing load balancing of work queues via a dispatcher that shifts work items between worker threads. The dispatcher can be added to the kernel and can monitor work item workload histories to estimate the workload that each work item will add to a thread that it is scheduled for. Where a workload for a given processor is predicted to trigger performance scaling of that processor, the dispatcher can reschedule one or more work items from the scheduled or default work thread to another work thread. The another work thread can be selected such that the addition of the work item will not trigger performance scaling of the another work thread.

Abstract: Systems and methods for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) are presented. A cache memory of the multi-core SoC not being accessed by other components of the SoC is identified and a number of dirty cache lines present in the cache memory is determined. For a low power mode of the core, an entry latency based on the number of dirty cache lines is determined, and an exit latency is determined. An entry power cost for the low power mode is also determined based on the number of dirty cache lines A determination is made whether the low power mode for the cache memory results in a power savings over an active mode for the cache memory based at least on the entry power cost and the entry latency of the cache memory entering the first power mode.

Abstract: Systems, methods, and apparatus are herein disclosed for performing load balancing of work queues via a dispatcher that shifts work items between worker threads. The dispatcher can be added to the kernel and can monitor work item workload histories to estimate the workload that each work item will add to a thread that it is scheduled for. Where a workload for a given processor is predicted to trigger performance scaling of that processor, the dispatcher can reschedule one or more work items from the scheduled or default work thread to another work thread. The another work thread can be selected such that the addition of the work item will not trigger performance scaling of the another work thread.

Abstract: Systems and methods for dynamically adjusting an input parameter, such as power supply level, to a shared power domain in a portable computing device are disclosed. The power domain includes a plurality of processing resources that share the power source. The power supply level is reduced based on a critical core vote pool derived from votes from the plurality of processing resources. The critical core vote pool is narrowed from all the votes by disqualifying votes based on the operating status of the associated processing resources. For example, because inactive processing resources may be unaffected by a change in the voltage level to the shared domain, and because certain active processing resources are in a position to adjust to a power change dictated by another processing resource, such processing resources may be considered noncritical and their votes disqualified from consideration.

Abstract: A method and computing apparatus for controlling operation of hardware processing components are disclosed. The method may include receiving a data packet (e.g., a media frame) at the computing device, processing the data packet with a plurality of hardware components to display the data packet, and monitoring movement of the data packet among the hardware components. A time indication for each hardware component is generated that indicates when the data packet will be received, and a frequency of each of the hardware components is adjusted based upon when the frame will arrive to be processed.

Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.

Abstract: Systems and methods for dynamically adjusting an input parameter to a power domain in a portable computing device are disclosed. The power domain includes two or more processing resources that share a power source. Dynamic use of the two or more processing resources creates an opportunity to adjust the input parameter when a status change associated with a processing resource in the power domain occurs. A controller in the power domain includes logic that responds to a status indicator associated with a respective processing resource in the power domain by generating a control signal that directs a device to adjust one or both of input voltage and clock frequency.

Abstract: Systems and methods that allow for dynamic quality of service (QoS) levels for an application processor in a multi-core on-chip system (SoC) in a portable computing device (PCD) are presented. During operation of the PCD an operational load of a co-processor of the SoC is determined, where the co-processor is in communication with an application processor of the SoC. Based on the determined load, the co-processor determines a QoS level required from the application processor. The QoS level is communicated to the application processor. The application processor determines whether it can implement power optimization measures, such as entering into a low power mode (LPM), based at least in part on the dynamically communicated QoS level from the co-processor. The present disclosure provides a cost effective ability to reduce power consumption in PCDs implementing one or more cores or CPUs that are dependent upon the application processor.

Abstract: This disclosure describes systems, methods, and apparatus for reducing power consumption and improving performance on a computing device. A method includes scheduling, with a driver on the computing device, one or more activity times that indicate when the driver will be active and storing the one or more activity times that indicate when the driver will be active. When a request to suspend a system of the computing device is received, the stored activity times are accessed to identify when the driver will be active, and a determination is made whether any of the one or more activity times is scheduled to occur within a suspend time window. If the driver will not be active during the suspend time window, suspension of the system is initiated.

Abstract: A method and apparatus for adjusting buffer size are provided. The method may comprise downloading a media file onto a media-player device, and then detecting, by the media-player device, the speed of the downloading. The method may further comprise transferring a first buffer packet of media content from the media file to a media processor. Then, the method may comprise providing and interrupt signal from the media processor, that indicated that the media content of first buffer packet has reached a lower media content threshold, and transferring, to the media processor, in response to the interrupt signal, one or more variably-sized buffer packets that are adjusted in size based on the speed of the downloading.

Abstract: Systems and methods for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) are presented. A core of the multi-core SoC entering an idle state is identified. For a low power mode of the core, an entry power cost of the core and an exit power cost of the core is calculated. A working set size for a cache associated with the core is also calculated. A latency for the cache to exit the low power mode of the core is calculated using the working set size. Finally, a determination is made whether the low power mode for the core results in a power savings over an active mode for the core based in part on the entry and exit power costs of the core, and the latency of the cache exiting the low power mode.

Abstract: Systems and methods for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) are presented. A cache memory of the multi-core SoC not being accessed by other components of the SoC is identified and a number of dirty cache lines present in the cache memory is determined. For a low power mode of the core, an entry latency based on the number of dirty cache lines is determined, and an exit latency is determined. An entry power cost for the low power mode is also determined based on the number of dirty cache lines A determination is made whether the low power mode for the cache memory results in a power savings over an active mode for the cache memory based at least on the entry power cost and the entry latency of the cache memory entering the first power mode.

Abstract: This disclosure describes systems, methods, and apparatus for reducing power consumption and improving performance on a computing device. A method includes scheduling, with a driver on the computing device, one or more activity times that indicate when the driver will be active and storing the one or more activity times that indicate when the driver will be active. When a request to suspend a system of the computing device is received, the stored activity times are accessed to identify when the driver will be active, and a determination is made whether any of the one or more activity times is scheduled to occur within a suspend time window. If the driver will not be active during the suspend time window, suspension of the system is initiated.

Abstract: A method and computing apparatus for controlling operation of hardware processing components are disclosed. The method may include receiving a data packet (e.g., a media frame) at the computing device, processing the data packet with a plurality of hardware components to display the data packet, and monitoring movement of the data packet among the hardware components. A time indication for each hardware component is generated that indicates when the data packet will be received, and a frequency of each of the hardware components is adjusted based upon when the frame will arrive to be processed.

Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.