Patents by Inventor Sravana Kumar GOLI

Sravana Kumar GOLI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979116
    Abstract: In described examples, a circuit includes an integrator. The integrator generates a first signal responsive to an input signal. A trigger circuit is coupled to the integrator and receives the first signal. A charge dump circuit is coupled to the integrator and the trigger circuit. The trigger circuit modifies configuration of the charge dump circuit and the integrator when the first signal is greater than a first threshold.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: May 7, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Sravana Kumar Goli, Nagesh Surendranath, Srinivas Bangalore Seshadri, Sandeep Kesrimal Oswal
  • Publication number: 20240072738
    Abstract: In at least one example, a circuit includes an amplifier, a first feedback loop, and a second feedback loop. The amplifier includes an amplifier input and an amplifier output. The first feedback loop includes a first feedback capacitor and a first switch. The first feedback loop is coupled between the amplifier input and the amplifier output. The first feedback capacitor is coupled to the amplifier output through the first switch. The second feedback loop includes a second feedback capacitor and a second switch. The second feedback loop is coupled in parallel with the first feedback loop between the amplifier input and the amplifier output. The second feedback capacitor is coupled to the amplifier input and to the first feedback capacitor through the second switch.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Sravana Kumar GOLI, Nagesh SURENDRANATH
  • Patent number: 11901864
    Abstract: A circuit includes an amplifier having an input and an output. A voltage comparator has an input and first and second outputs. The input of the voltage comparator is coupled to the output of the amplifier. A variable capacitor circuit is coupled between the input and the output of the amplifier and is coupled to the first output of the voltage comparator. A charge dump circuit has an input and an output. The input of the charge dump circuit is coupled to the second output of the voltage comparator. The output of the charge dump circuit is coupled to the input of the amplifier.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: February 13, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Sravana Kumar Goli, Nagesh Surendranath, Saugata Datta, Sandeep Oswal
  • Patent number: 11528388
    Abstract: In described examples, a circuit includes an integrator. The integrator receives an input signal. A first sampling network is coupled to the integrator and generates a signal voltage. A second sampling network is coupled to the integrator and generates a pixel sampled noise voltage. The pixel sampled noise voltage generated in a previous cycle is subtracted from the signal voltage generated in a current cycle to generate a true signal voltage.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: December 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nagesh Surendranath, Sravana Kumar Goli
  • Publication number: 20220209722
    Abstract: In described examples, a circuit includes an integrator. The integrator generates a first signal responsive to an input signal. A trigger circuit is coupled to the integrator and receives the first signal. A charge dump circuit is coupled to the integrator and the trigger circuit. The trigger circuit modifies configuration of the charge dump circuit and the integrator when the first signal is greater than a first threshold.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Inventors: Sravana Kumar Goli, Nagesh Surendranath, Srinivas Bangalore Seshadri, Sandeep Kesrimal Oswal
  • Publication number: 20220021789
    Abstract: In described examples, a circuit includes an integrator. The integrator receives an input signal. A first sampling network is coupled to the integrator and generates a signal voltage. A second sampling network is coupled to the integrator and generates a pixel sampled noise voltage. The pixel sampled noise voltage generated in a previous cycle is subtracted from the signal voltage generated in a current cycle to generate a true signal voltage.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 20, 2022
    Inventors: Nagesh Surendranath, Sravana Kumar Goli
  • Patent number: 11152903
    Abstract: In accordance with one embodiment, an apparatus includes a first amplifier having a noninverting input, an inverting input and an output. The noninverting input is coupled to a first ground reference. The inverting input is coupled to an output of an external sensor. The apparatus also includes a second amplifier having a noninverting input, an inverting input and an output. The noninverting input is coupled to the first ground reference. The inverting input is coupled to the power supply through a first variable capacitor and to the second ground reference through a second variable capacitor. The output is coupled to the inverting input of the first amplifier. The external sensor is coupled to a third ground reference, and the first amplifier and second amplifier are coupled to the second ground reference.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nagesh Surendranath, Shriram Mahendra Devi, Sravana Kumar Goli
  • Publication number: 20210119594
    Abstract: In accordance with one embodiment, an apparatus includes a first amplifier having a noninverting input, an inverting input and an output. The noninverting input is coupled to a first ground reference. The inverting input is coupled to an output of an external sensor. The apparatus also includes a second amplifier having a noninverting input, an inverting input and an output. The noninverting input is coupled to the first ground reference. The inverting input is coupled to the power supply through a first variable capacitor and to the second ground reference through a second variable capacitor. The output is coupled to the inverting input of the first amplifier. The external sensor is coupled to a third ground reference, and the first amplifier and second amplifier are coupled to the second ground reference.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 22, 2021
    Inventors: Nagesh Surendranath, Shriram Mahendra Devi, Sravana Kumar Goli
  • Patent number: 10484636
    Abstract: An active pixel sensor a plurality of sensor pixels disposed in a row, a plurality of sensor pixels in a column, and steering circuitry coupled to each of the sensor pixels. Each of the sensor pixels includes a first pixel circuit, and a second pixel circuit. For each of the sensor pixels, the steering circuitry includes a first switch, a second switch, a third switch, and a fourth switch. The first switch and the second switch are connected in series to route an input signal to the first pixel circuit. The third switch and a fourth switch are connected in parallel to route the input signal to the second pixel circuit.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: November 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sravana Kumar Goli, Jeevan Mithra, Nagesh Surendranath, Sandeep Kesrimal Oswal
  • Publication number: 20190297294
    Abstract: An active pixel sensor a plurality of sensor pixels disposed in a row, a plurality of sensor pixels in a column, and steering circuitry coupled to each of the sensor pixels. Each of the sensor pixels includes a first pixel circuit, and a second pixel circuit. For each of the sensor pixels, the steering circuitry includes a first switch, a second switch, a third switch, and a fourth switch. The first switch and the second switch are connected in series to route an input signal to the first pixel circuit. The third switch and a fourth switch are connected in parallel to route the input signal to the second pixel circuit.
    Type: Application
    Filed: March 20, 2018
    Publication date: September 26, 2019
    Inventors: Sravana Kumar GOLI, Jeevan MITHRA, Nagesh SURENDRANATH, Sandeep Kesrimal OSWAL