Patents by Inventor Sravanthi Tangeda
Sravanthi Tangeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11494212Abstract: Technologies for adaptive platform resource management include a compute node to manage a processor core mapping scheme between virtual machines (VMs) and a virtual switch of the compute node via a set of virtual ports. The virtual switch is also coupled to a network interface controller (NIC) of the compute node via another set of virtual ports. Each of the VMs is configured to either provide ingress or egress to the NIC or provide ingress/egress across the VMs, via the virtual ports. The virtual ports for providing ingress or egress to the NIC are pinned to a same processor core of a processor of the compute node, and each of the virtual ports for providing ingress and/or egress across the VMs are pinned to a respective processor core of the processor such that data is transferred across VMs by coupled virtual ports that are pinned to the same processor core.Type: GrantFiled: September 27, 2018Date of Patent: November 8, 2022Assignee: Intel CorporationInventors: Ranganath Sunku, Dinesh Kumar, Irene Liew, Kavindya Deegala, Sravanthi Tangeda
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Publication number: 20190042298Abstract: Technologies for adaptive platform resource management include a compute node to manage a processor core mapping scheme between virtual machines (VMs) and a virtual switch of the compute node via a set of virtual ports. The virtual switch is also coupled to a network interface controller (NIC) of the compute node via another set of virtual ports. Each of the VMs is configured to either provide ingress or egress to the NIC or provide ingress/egress across the VMs, via the virtual ports. The virtual ports for providing ingress or egress to the NIC are pinned to a same processor core of a processor of the compute node, and each of the virtual ports for providing ingress and/or egress across the VMs are pinned to a respective processor core of the processor such that data is transferred across VMs by coupled virtual ports that are pinned to the same processor core.Type: ApplicationFiled: September 27, 2018Publication date: February 7, 2019Inventors: Ranganath Sunku, Dinesh Kumar, Irene Liew, Kavindya Deegala, Sravanthi Tangeda
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Patent number: 10158578Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.Type: GrantFiled: September 19, 2016Date of Patent: December 18, 2018Assignee: Intel CorporationInventors: Cristian Florin Dumitrescu, Andrey Chilikin, Pierre Laurent, Kannan Babu Ramia, Sravanthi Tangeda
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Patent number: 10091122Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.Type: GrantFiled: December 31, 2016Date of Patent: October 2, 2018Assignee: Intel CorporationInventors: Cristian Florin Dumitrescu, Andrey Chilikin, Pierre Laurent, Kannan Babu Ramia, Sravanthi Tangeda
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Publication number: 20170149678Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.Type: ApplicationFiled: December 31, 2016Publication date: May 25, 2017Applicant: INTEL CORPORATIONInventors: Cristian Florin Dumitrescu, Andrey Chilikin, Pierre Laurent, Kannan Babu Ramia, Sravanthi Tangeda
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Publication number: 20170070356Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.Type: ApplicationFiled: September 19, 2016Publication date: March 9, 2017Applicant: INTEL CORPORATIONInventors: Cristian Florin Dumitrescu, Andrey Chilikin, Pierre Laurent, Kannan Babu Ramia, Sravanthi Tangeda
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Patent number: 9450881Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.Type: GrantFiled: December 27, 2013Date of Patent: September 20, 2016Assignee: Intel CorporationInventors: Cristian Florin Dumitrescu, Andrey Chilikin, Pierre Laurent, Kannan Babu Ramia, Sravanthi Tangeda
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Publication number: 20150016266Abstract: One embodiment provides a network device. The network device includes a a processor including at least one processor core; a network interface configured to transmit and receive packets at a line rate; a memory configured to store a scheduler hierarchical data structure; and a scheduler module. The scheduler module is configured to prefetch a next active pipe structure, the next active pipe structure included in the hierarchical data structure, update credits for a current pipe and an associated subport, identify a next active traffic class within the current pipe based, at least in part, on a current pipe data structure, select a next queue associated with the identified next active traffic class, and schedule a next packet from the selected next queue for transmission by the network interface if available traffic shaping token bucket credits and available traffic class credits are greater than or equal to a next packet credits.Type: ApplicationFiled: December 27, 2013Publication date: January 15, 2015Inventors: Cristian Florin Dumitrescu, Andrey Chilikin, Pierre Laurent, Kannan Babu Ramia, Sravanthi Tangeda