Abstract: A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.

Abstract: Disclosed is a row address comparator with voltage level shifting and latching functionality and including: an evaluation section for comparing two row addresses in a first voltage domain and outputting an initial match signal in a second voltage domain; and a latch section for outputting a latched final match signal based on the initial match signal. The comparator employs a first clock signal (CLK1), a second clock signal (CLK2) that is different from CLK1 and a third clock signal (CLK3) that is inverted with respect to CLK2. CLKs 1 and 2 control pre-charge and evaluation operations within the evaluation section with CLK2 being set to minimize hold time. CLKs 2 and 3 control the latch operation within the latch section. Feedback loops in both sections enhance performance. Also disclosed are a control circuit that incorporates the comparator and a method for implementing row redundancy in a memory.

Abstract: A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.

Abstract: Disclosed is a row address comparator with voltage level shifting and latching functionality and including: an evaluation section for comparing two row addresses in a first voltage domain and outputting an initial match signal in a second voltage domain; and a latch section for outputting a latched final match signal based on the initial match signal. The comparator employs a first clock signal (CLK1), a second clock signal (CLK2) that is different from CLK1 and a third clock signal (CLK3) that is inverted with respect to CLK2. CLKs 1 and 2 control pre-charge and evaluation operations within the evaluation section with CLK2 being set to minimize hold time. CLKs 2 and 3 control the latch operation within the latch section. Feedback loops in both sections enhance performance. Also disclosed are a control circuit that incorporates the comparator and a method for implementing row redundancy in a memory.

Abstract: A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.

Abstract: A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.

Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.

Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.

Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.

Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.

Abstract: The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.

Abstract: The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.