Patents by Inventor Sreeker Dundigal
Sreeker Dundigal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230411956Abstract: Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor). The current through the resistor creates a voltage drop across the resistor, which reduces the voltage seen by the protected transistor. In certain aspects, the current path is provided by an ESD circuit coupled to a node between the resistor and the transistor. In certain aspects, the current path is created by turning on the transistor during the ESD event with a trigger device.Type: ApplicationFiled: August 2, 2023Publication date: December 21, 2023Inventors: Sreeker DUNDIGAL, Reza JALILIZEINALI, Krishna Chaitanya CHILLARA, Wen-Yi CHEN
-
Patent number: 11575259Abstract: An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad.Type: GrantFiled: July 8, 2021Date of Patent: February 7, 2023Assignee: QUALCOMM INCORPORATEDInventors: Wen-Yi Chen, Reza Jalilizeinali, Sreeker Dundigal, Krishna Chaitanya Chillara, Gregory Lynch
-
Publication number: 20230008489Abstract: An ESD protection circuit has a driver transistor with a drain that is coupled to an I/O pad of an IC device and a source that is coupled to a first rail of a power supply in the IC device, and a diode that couples the I/O pad to the first rail and that is configured to be reverse-biased when a rated voltage is applied to the I/O pad. The rated voltage lies within a nominal operating range for voltage levels defined for the input/output pad. The ESD protection circuit has a gate pull transistor that couples a gate of the driver transistor to the I/O pad or the first rail. The gate pull transistor may be configured to present a high impedance path between the gate of the driver transistor and the I/O pad or the first rail when the rated voltage is applied to the I/O pad.Type: ApplicationFiled: July 8, 2021Publication date: January 12, 2023Inventors: Wen-Yi CHEN, Reza JALILIZEINALI, Sreeker DUNDIGAL, Krishna Chaitanya CHILLARA, Gregory LYNCH
-
Publication number: 20210408786Abstract: Exemplary electrostatic discharge (ESD) circuit schemes are provided according to various aspects of the present disclosure. In certain aspects, a current path is created during an ESD event that causes current to flow through a resistor coupled to a protected transistor (e.g., a driver transistor). The current through the resistor creates a voltage drop across the resistor, which reduces the voltage seen by the protected transistor. In certain aspects, the current path is provided by an ESD circuit coupled to a node between the resistor and the transistor. In certain aspects, the current path is created by turning on the transistor during the ESD event with a trigger device.Type: ApplicationFiled: June 22, 2021Publication date: December 30, 2021Inventors: Sreeker DUNDIGAL, Reza JALILIZEINALI, Krishna Chaitanya CHILLARA, Wen-Yi CHEN
-
Publication number: 20210407990Abstract: A chip includes a pad and a driver having an output coupled to the pad. The chip also includes one or more diodes coupled between the pad and a ground bus, wherein the one or more diodes are in a forward direction from the pad to the ground bus.Type: ApplicationFiled: June 22, 2021Publication date: December 30, 2021Inventors: Sreeker DUNDIGAL, Reza JALILIZEINALI, Krishna Chaitanya CHILLARA, Wen-Yi CHEN
-
Patent number: 10424921Abstract: A semiconductor die including: a die-to-die interface including an input/output (I/O) circuitry area and an electrical contact area; wherein the electrical contact area includes an array of electrical contacts disposed on a side of the semiconductor die; and wherein the I/O circuitry area includes a plurality of drivers, each of the drivers coupled to at least one electrical contact in the electrical contact area, and a plurality of electrostatic discharge (ESD) protection devices, each of the ESD protection devices coupled to a respective driver, further wherein the I/O circuitry area and the electrical contact area are separated in a top-down view of the semiconductor die.Type: GrantFiled: February 16, 2017Date of Patent: September 24, 2019Assignee: QUALCOMM IncorporatedInventors: Kenneth Dubowski, Luverne Ray Peterson, Thomas Bryan, Stephen Knol, Sreeker Dundigal, Alvin Loke
-
Patent number: 10298010Abstract: A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit includes detecting an electrostatic discharge event. The method also includes selectively disengaging a power supply terminal from a pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event. The method further includes selectively disengaging a ground terminal from the pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event.Type: GrantFiled: March 31, 2016Date of Patent: May 21, 2019Assignee: QUALCOMM IncorporatedInventors: Eugene Robert Worley, Reza Jalilizeinali, Sreeker Dundigal, Wen-Yi Chen, Krishna Chaitanya Chillara, Taeghyun Kang
-
Publication number: 20180233907Abstract: A semiconductor die including: a die-to-die interface including an input/output (I/O) circuitry area and an electrical contact area; wherein the electrical contact area includes an array of electrical contacts disposed on a side of the semiconductor die; and wherein the I/O circuitry area includes a plurality of drivers, each of the drivers coupled to at least one electrical contact in the electrical contact area, and a plurality of electrostatic discharge (ESD) protection devices, each of the ESD protection devices coupled to a respective driver, further wherein the I/O circuitry area and the electrical contact area are separated in a top-down view of the semiconductor die.Type: ApplicationFiled: February 16, 2017Publication date: August 16, 2018Inventors: Kenneth Dubowski, Luverne Ray Peterson, Thomas Bryan, Stephen Knol, Sreeker Dundigal, Alvin Loke
-
Patent number: 10032763Abstract: In an aspect of the disclosure, a MOS device for using bulk cross-coupled thin-oxide decoupling capacitor is provided. The MOS device may include a pMOS transistor and an nMOS transistor. The MOS device may include a first set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The first set of transistor body connections may couple a first voltage source to the pMOS transistor body. The first set of transistor body connections may further couple a second voltage source to the nMOS transistor body. The MOS device may include a second set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The second set of transistor body connections may couple the nMOS transistor gate to the pMOS transistor body. The second set of transistor body connections may further couple the pMOS transistor gate to the nMOS transistor body.Type: GrantFiled: June 2, 2016Date of Patent: July 24, 2018Assignee: QUALCOMM IncorporatedInventors: Albert Kumar, Hai Dang, Sreeker Dundigal, Vasisht Vadi
-
Publication number: 20170352651Abstract: In an aspect of the disclosure, a MOS device for using bulk cross-coupled thin-oxide decoupling capacitor is provided. The MOS device may include a pMOS transistor and an nMOS transistor. The MOS device may include a first set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The first set of transistor body connections may couple a first voltage source to the pMOS transistor body. The first set of transistor body connections may further couple a second voltage source to the nMOS transistor body. The MOS device may include a second set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The second set of transistor body connections may couple the nMOS transistor gate to the pMOS transistor body. The second set of transistor body connections may further couple the pMOS transistor gate to the nMOS transistor body.Type: ApplicationFiled: June 2, 2016Publication date: December 7, 2017Inventors: Albert KUMAR, Hai DANG, Sreeker DUNDIGAL, Vasisht VADI
-
Publication number: 20170288398Abstract: A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit includes detecting an electrostatic discharge event. The method also includes selectively disengaging a power supply terminal from a pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event. The method further includes selectively disengaging a ground terminal from the pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: Eugene Robert WORLEY, Reza JALILIZEINALI, Sreeker DUNDIGAL, Wen-Yi CHEN, Krishna Chaitanya CHILLARA, Taeghyun KANG
-
Patent number: 9406627Abstract: A system interconnect includes a first resistor-capacitor (RC) clamp having a first RC time constant. The system interconnect also includes second RC clamps having a second RC time constant. The first and second RC clamps are arranged along the system interconnect. In addition, the first RC time constant is different from the second RC time constant.Type: GrantFiled: September 26, 2013Date of Patent: August 2, 2016Assignee: QUALCOMM INCORPORATEDInventors: Eugene Robert Worley, Reza Jalilizeinali, Sreeker Dundigal
-
Publication number: 20150249334Abstract: Techniques for reducing leakage current during normal operation of an electrostatic discharge (ESD) circuit are described herein. In one embodiment, a circuit comprises an internal circuit and an electrostatic discharge (ESD) rail clamp coupled in parallel to the internal circuit and between first and second power supply rails. The ESD rail clamp is operable to shunt ESD current from the first power supply rail to the second power supply rail via a low resistance shunt path. The ESD rail clamp comprises an ESD trigger circuit configured to detect an ESD event and a plurality of discharging transistors coupled in series. The ESD trigger circuit is configured to turn off the discharging transistors during normal operation and to turn on the discharging transistors to form the low resistance shunt path in response to detection of the ESD event.Type: ApplicationFiled: February 28, 2014Publication date: September 3, 2015Applicant: QUALCOMM INCORPORATEDInventors: Wen-Yi Chen, Sreeker Dundigal, Reza Jalilizeinali, Eugene Robert Worley
-
Patent number: 9083176Abstract: In a particular embodiment, a circuit includes a power supply, a ground, and a clamping transistor circuit coupled to the power supply and to the ground. The circuit further includes a disable clamp circuit. The disable clamp circuit is coupled to the power supply and is responsive to a second power supply input to selectively disable the clamping transistor circuit by modifying a charging current applied to a capacitor of the clamping transistor circuit. In a particular embodiment, modifying the charging current includes enabling a second charging path. Enabling the second charging path enables charging the capacitor at a higher charging rate than a charging rate associated with charging the capacitor via a first charging path.Type: GrantFiled: January 11, 2013Date of Patent: July 14, 2015Assignee: QUALCOMM IncorporatedInventors: Eugene Robert Worley, Sreeker Dundigal, Evan Siansuri, Reza Jalilizeinali, Michael Brunolli
-
Publication number: 20150084161Abstract: A system interconnect includes a first resistor-capacitor (RC) clamp having a first RC time constant. The system interconnect also includes second RC clamps having a second RC time constant. The first and second RC clamps are arranged along the system interconnect. In addition, the first RC time constant is different from the second RC time constant.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Applicant: QUALCOMM IncorporatedInventors: Eugene Robert WORLEY, Reza JALILIZEINALI, Sreeker DUNDIGAL
-
Publication number: 20140198414Abstract: In a particular embodiment, a circuit includes a power supply, a ground, and a clamping transistor circuit coupled to the power supply and to the ground. The circuit further includes a disable clamp circuit. The disable clamp circuit is coupled to the power supply and is responsive to a second power supply input to selectively disable the clamping transistor circuit by modifying a charging current applied to a capacitor of the clamping transistor circuit. In a particular embodiment, modifying the charging current includes enabling a second charging path. Enabling the second charging path enables charging the capacitor at a higher charging rate than a charging rate associated with charging the capacitor via a first charging path.Type: ApplicationFiled: January 11, 2013Publication date: July 17, 2014Applicant: QUALCOMM IncorporatedInventors: Eugene Robert Worley, Sreeker Dundigal, Evan Siansuri, Reza Jalilizeinali, Michael Brunolli
-
Patent number: 8665570Abstract: Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.Type: GrantFiled: March 30, 2011Date of Patent: March 4, 2014Assignee: QUALCOMM IncorporatedInventors: Reza Jalilizeinali, Eugene R. Worley, Evan Siansuri, Sreeker Dundigal
-
Patent number: 8184414Abstract: A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.Type: GrantFiled: July 30, 2008Date of Patent: May 22, 2012Assignee: QUALCOMM IncorporatedInventors: Reza Jalilizeinali, Sreeker Dundigal, Vivek Mohan, Thomas R. Toms
-
Publication number: 20120074496Abstract: Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance.Type: ApplicationFiled: March 30, 2011Publication date: March 29, 2012Applicant: QUALCOMM IncorporatedInventors: Reza Jalilizeinali, Eugene R. Worley, Evan Siansuri, Sreeker Dundigal
-
Patent number: 8040645Abstract: A protection system implemented on one die of a multi-die package provides a discharge path for excess voltages incurred on one or more other die of the package. Ground paths are provided for certain circuitry in the package that have high noise-sensitivity, and ground paths are provided for certain circuitry in the package that have low noise-sensitivity relative to the high noise-sensitivity circuitry. The grounds of high noise-sensitivity circuitry of multiple die are shorted together, resulting in a common high noise-sensitivity ground. The grounds of low noise-sensitivity circuitry of multiple die are shorted together, resulting in a common low noise-sensitivity ground. A pre-designated removable path is included on the package external to the die, which shorts the common high noise-sensitivity ground and the common low noise-sensitivity ground. The removable path may be removed during manufacturing, if noise present on the shorted grounds results in unacceptable performance degradation.Type: GrantFiled: August 12, 2008Date of Patent: October 18, 2011Assignee: QUALCOMM IncorporatedInventors: Reza Jalilizeinali, Sreeker Dundigal, Vivek Mohan