Abstract: A method and system for reducing power consumption while improving efficiency of a memory management unit of a portable computing device include determining if data of a memory request exists within a first memory element external to the memory management unit. The first memory element may include a cache. If the data of the memory request does not exist within the first memory element, then a magnitude of a burst length value of the memory request may be determined. Subsequently, a page table walk may be conducted with a second memory element, such as DDR (double-data rate) memory, that corresponds with the magnitude of the burst length value of second memory element (DDR). Each memory request may include a descriptor. The descriptor may have a reserved field region that includes a pre-fetch hint which indicates whether next descriptors in the second memory element are valid or not.

Abstract: A method and system for reducing power consumption while improving efficiency of a memory management unit of a portable computing device are described. The method and system include determining if data of a memory request exists within a first memory element external to the memory management unit. The first memory element may include a cache. If the data of the memory request does not exist within the first memory element, then a magnitude of a burst length value of the memory request may be determined. Subsequently, a page table walk may be conducted with a second memory element, such as DDR memory, that corresponds with the magnitude of the burst length value of the memory request. Each memory request may include a descriptor. The descriptor may have a reserved field region that includes a pre-fetch hint which indicates whether next descriptors in the second memory element are valid or not.

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.

Abstract: Memory systems and accessing methods are disclosed. In one embodiment, a method of accessing a memory device includes accessing a first end of the memory device regarding a first data type, and accessing a second end of the memory device regarding a second data type.

Abstract: A semiconductor device coupled to input/output pins includes a first core to operate a first function and a second core to operate a second function. A multiplexer is arranged to set the input/output pins to the first function or to the second function, and an arbiter is configured to receive requests from the cores to use the input/output pins and to grant use of the input/output pins to a selected core. A register is arranged to store a value indicative of a delay to be applied by the arbiter when granting use of the input/output pins to the second core.