Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: A method, system, and computer readable medium for converting a series of computer executable instructions in control flow graph form into an intermediate representation, of a type similar to Static Single Assignment (SSA), used in the compiler arts. The indeterminate representation may facilitate compilation optimizations such as constant propagation, sparse conditional constant propagation, dead code elimination, global value numbering, partial redundancy elimination, strength reduction, and register allocation. The method, system, and computer readable medium are capable of operating on the control flow graph to construct an SSA representation in parallel, thus exploiting recent advances in multi-core processing and massively parallel computing systems. Other embodiments may be employed, and other embodiments are described and claimed.

Abstract: Profile information can be used to target read operations that cause a substantial portion of misses in a program. A software value prediction technique that utilizes latency and is applied to the targeted read operations facilitates aggressive speculative execution without significant performance impact and without hardware support. A software value predictor issues prefetches for targeted read operations during speculative execution, and utilizes values from these prefetches during subsequent speculative execution, since the earlier prefectches should have completed, to update a software value prediction structure(s). Such a software based value prediction technique allows for aggressive speculative execution without the overhead of a hardware value predictor.

Abstract: A processor virtualization abstracts the behavior of a processor instruction set architecture from an underlying micro-architecture implementation. It is capable of running any processor instruction set architecture compatible software on any micro-architecture implementation. A system wide dynamic binary translator translates source system programs to target programs and manages the execution of those target programs. It also provides the necessary and sufficient infrastructure requires to render multi-core processor virtualization.

Abstract: Disclosed is a method for eliminating dead code from a computer program using an operands graph generated from a flow graph of a computer program. In one embodiment of the present invention, the operands graph is traversed for any unused operands. Upon detection of any,unused operands, the instructions defining the unused operands are removed from execution.

Abstract: One embodiment of the present invention provides a system that uses value speculation to break constraining dependencies in loops. The system operates by first identifying a loop within a computer program, and then identifying a dependency on a long-latency operation within the loop that is likely to constrain execution of the loop. Next, the system breaks the dependency by modifying the loop to predict a value that will break the dependency, and then using the predicted value to speculatively execute subsequent loop instructions.

Abstract: One embodiment of the present invention provides a system that uses value speculation to break constraining dependencies in loops. The system operates by first identifying a loop within a computer program, and then identifying a dependency on a long-latency operation within the loop that is likely to constrain execution of the loop. Next, the system breaks the dependency by modifying the loop to predict a value that will break the dependency, and then using the predicted value to speculatively execute subsequent loop instructions.

Abstract: Disclosed is a method for eliminating dead code from a computer program using an operands graph generated from a flow graph of a computer program. In one embodiment of the present invention, the operands graph is traversed for any unused operands. Upon detection of any,unused operands, the instructions defining the unused operands are removed from execution.

Abstract: One embodiment of the present invention provides a system that redirects control flow of original code to transformed code. The system includes a computer processor with an instruction fetch unit that determines a next instruction to be executed by the processor. The system also includes a control redirection buffer, which indicates whether to conditionally redirect execution from a first instruction address to a second instruction address so that the transformed code at the second instruction address can be executed in place of the original code at the first instruction address.

Abstract: A method for optimizing an object file is described. The method includes simulating execution of an object file, where the object file includes a control transfer instruction having an undefined target, and modifying the object file to include an address space bridge section, where the address space bridge section is configured to define the undefined target. When the newly optimized object file is executed, the address space bridge is invoked and the target is mapped in memory in an original address space.