Abstract: A chip package includes a micro-link between components disposed on a substrate. The micro-link may be an ultra-short multi-conductor transmission line with shared reference planes that results in a distribution of impedance values. Furthermore, the composite signal traces in the transmission line each can support communication of one symbol at a time by ensuring that multiple reflections reach a substantial fraction of a steady-state value within a symbol time. In this way, the micro-link may facilitate continued scaling of the communication bandwidth between the components with low latency to increase the performance of computer systems that include the chip package.

Abstract: A chip package includes a micro-link between components disposed on a substrate. The micro-link may be an ultra-short multi-conductor transmission line with shared reference planes that results in a distribution of impedance values. Furthermore, the composite signal traces in the transmission line each can support communication of one symbol at a time by ensuring that multiple reflections reach a substantial fraction of a steady-state value within a symbol time. In this way, the micro-link may facilitate continued scaling of the communication bandwidth between the components with low latency to increase the performance of computer systems that include the chip package.

Abstract: A method including obtaining an operational status of a first processor core, where the first processor core is associated with a plurality of processor cores located on a chip; configuring a first IO block of a package design based on the operational status of the first processor core, where the package design is based on a fully functional chip; and configuring a stackup of the package design after configuring the first IO block for use with the chip.

Abstract: A method including obtaining an operational status of a first processor core, where the first processor core is associated with a plurality of processor cores located on a chip; configuring a first IO block of a package design based on the operational status of the first processor core, where the package design is based on a fully functional chip; and configuring a stackup of the package design after configuring the first IO block for use with the chip.

Abstract: A method including obtaining an operational status of a first processor core, where the first processor core is associated with a plurality of processor cores located on a chip; configuring a first IO block of a package design based on the operational status of the first processor core, where the package design is based on a fully functional chip; and configuring a stackup of the package design after configuring the first IO block for use with the chip.

Abstract: A method including obtaining an operational status of a first processor core, where the first processor core is associated with a plurality of processor cores located on a chip; configuring a first IO block of a package design based on the operational status of the first processor core, where the package design is based on a fully functional chip; and configuring a stackup of the package design after configuring the first IO block for use with the chip.

Abstract: The present application describes a method and an apparatus for characterizing a conductive plane using multipoint measurement. In an embodiment of the present invention, a known current is injected in the conductive plane using multipoint probes and voltage is measured using multipoint probes. The electrical characteristics of the plane can be determined using the values of the known current, measured voltage and the distance between the probes. In an embodiment of the present invention, the conductive plane is integrated in a semiconductor package of an integrated circuit and the value of the known current is determined based on the actual current that can be provided by the integrated circuit during normal operation.

Abstract: The present application describes a method and an apparatus for characterizing a conductive plane using multipoint measurement. In an embodiment of the present invention, a known current is injected in the conductive plane using multipoint probes and voltage is measured using multipoint probes. The electrical characteristics of the plane can be determined using the values of the known current, measured voltage and the distance between the probes. In an embodiment of the present invention, the conductive plane is integrated in a semiconductor package of an integrated circuit and the value of the known current is determined based on the actual current that can be provided by the integrated circuit during normal operation.