Abstract: A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels. A transmitter system and a receiver system are described for the communication system.

Abstract: A receiver that easily receives signals from transmission channels having long cable lengths is presented. The receiver includes an analog pre-filter that removes distortions and intersymbol interference from a predetermined transmission channel. The analog pre-filter is coupled with a digital receiver that provides digital equalization. The combination of analog equalization with digital equalization allows for simplified digital equalization while retaining the versatility of digital signal processing.

Abstract: A receiver that easily receives signals from transmission channels having long cable lengths is presented. The receiver includes an analog pre-filter that removes distortions and intersymbol interference from a predetermined transmission channel. The analog pre-filter is coupled with a digital receiver that provides digital equalization. The combination of analog equalization with digital equalization allows for simplified digital equalization while retaining the versatility of digital signal processing.

Abstract: An analog equalizer (613 and 614) adaptively equalizes an input analog signal affected with intersymbol interference (“ISI”), or an intermediate analog signal generated therefrom, to produce a filtered partially equalized analog signal with reduced ISI. An analog-to-digital converter (210) converts the filtered analog signal, or an intermediate analog signal generated therefrom, into an initial digital signal. A digital equalizer (212) adaptively equalizes the initial digital signal, or an intermediate digital signal generated therefrom, to produce an equalized digital signal as a stream of equalized digital values with further reduced ISI. An output decoder (605) decodes the equalized digital values, or intermediate digital values generated therefrom, into a stream of symbols.

Abstract: Analog echo-cancelling circuitry (611 and 627) operates on an input analog signal that includes an echo of an output signal, or on an analog signal generated from the input signal, to produce an analog signal with reduced echo. An analog-to-digital converter (210) converts the echo-reduced analog signal, or an analog signal generated therefrom, into a digital signal. Digital echo-cancelling circuitry (615 and 621) operates on the digital signal, or on a digital signal generated therefrom, to produce a digital signal with further reduced echo. An output decoder (605) decodes the echo-reduced digital signal, or a digital signal generated therefrom, into a stream of symbols. The echo-filtering characteristics of both echo-cancelling circuitries are typically adaptively adjusted during generation of the symbol stream. The analog echo-filtering characteristics may be adapted in response to information provided by operating on the echo-reduced digital signal or on a digital signal generated therefrom.

Abstract: A receiver for a multi-channel system such as a HDMI system is presented. In accordance with the present invention, the receiver receives one of the plurality of channels and includes an analog portion, a digital-to-analog converter, and a digital control block that provides digital control signals to the analog portion. Equalization can be accomplished partially or wholly in the analog domain and digitally controlled by a digital control loop. A digital equalizer can also be included. A decision feedback equalizer can be implemented that sums an analog output signal into the analog data stream. Timing recovery can be accomplished by digital control of a phase interpolator or delay locked loop that receives a plurality of phases from a timing circuit coupled to receive a clock signal.

Abstract: A receiver system contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605) arranged sequentially for processing an input analog signal (yk). The pre-filter produces a filtered analog signal (Zs) with reduced intersymbol interference. The converter provides analog-to-digital signal conversion. Digital equalization circuitry in the equalizer operates according to a transfer frmnction c - 1 ? z + c 0 + ? M i = 1 ? c i ? z - i to produce an equalized digital signal (a'k) as a stream of equalized digital values. Coefficients c?1 and c0 are fixed. Each other coefficient ci is adaptively chosen. The decoder converts the equalized digital values, or intermediate values generated therefrom, into a stream of symbols.

Abstract: An analog equalizer (613 and 614) adaptively equalizes an input analog signal affected with intersymbol interference (“ISI”), or an intermediate analog signal generated therefrom, to produce a filtered partially equalized analog signal with reduced ISI. An analog-to-digital converter (210) converts the filtered analog signal, or an intermediate analog signal generated therefrom, into an initial digital signal. A digital equalizer (212) adaptively equalizes the initial digital signal, or an intermediate digital signal generated therefrom, to produce an equalized digital signal as a stream of equalized digital values with further reduced ISI. An output decoder (605) decodes the equalized digital values, or intermediate digital values generated therefrom, into a stream of symbols.

Abstract: A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels. A transmitter system and a receiver system are described for the communication system.

Abstract: A transceiver according to the present invention receives data from a plurality of frequency separated transmission channels from a complementary transmitter and includes an interference filter for correcting for interference from transmitters other than the complementary transmitter. The interference filter, for example, can correct for near-end cross-talk and echo interference filtering and/or far-end crosstalk interference filtering is presented. A transceiver can include a transmitter portion and a receiver portion with one or more receivers coupled to receives signals in the plurality of frequency separated transmission channels. A baseband transmitter can be combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands).

Abstract: A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels. A transmitter system and a receiver system are described for the communication system.

Abstract: A sequence detector (1400-w) operating generally according to the Viterbi algorithm contains a branch metric generator (1402-w), comparison circuitry (1403-w), and symbol generation circuitry (1404, 1405, and 1406) for converting digital values of a detector input signal into a sequence of predefined symbols chosen from an alphabet of predefined symbols. The comparison circuitry provides soft output signals for correcting errors. The soft output signals include best and second-best state metrics (pk,w(i) and p2k,w(i)) and corresponding best and second-best comparison results (Dk,w(i) and D2k,w(i)). The symbol generation circuitry typically utilizes the best comparison results to generate a preliminary sequence of the predefined symbols, checks for error in the preliminary sequence, and utilizes the second-best comparison results in correcting any such error in the preliminary sequence so as to convert it into a final sequence of the predefined symbols.

Abstract: A transceiver according to the present invention receives data from a plurality of frequency separated transmission channels from a complementary transmitter and includes an interference filter for correcting for interference from transmitters other than the complementary transmitter. The interference filter, for example, can correct for near-end cross-talk and echo interference filtering and/or far-end crosstalk interference filtering is presented. A transceiver can include a transmitter portion and a receiver portion with one or more receivers coupled to receives signals in the plurality of frequency separated transmission channels. A baseband transmitter can be combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands).

Abstract: A sequence detector (1600-w) operating generally according to the Viterbi algorithm uses state reduction via division into symbol families to reduce the complexity of sequence detection. The sequence detector contains a branch metric generator (1402-w), comparison circuitry (1603-w), and symbol generation circuitry (1604, 1605-w, and 1606) for converting digital values of an input signal into a sequence of symbols chosen from an alphabet of predefined symbols allocated into multiple non-overlapping families each formed with a plurality of the predefined symbols. The branch metric generator makes intra-family branch selections, each of which is one of a plurality of branches respectively corresponding to a family's symbols, and generates corresponding branch metrics. The comparison circuitry determines state metrics and generates corresponding comparison results.

Abstract: A transceiver system according to the present invention transmits data utilizing the baseband and one or more frequency separated transmission bands. A baseband transmitter is combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. A baseband receiver is combined with one or more receivers that receive data from the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands). A transceiver circuit or chip according to the present invention includes a transmitter and a receiver and communicates with a corresponding transceiver chip. In some embodiments, one baseband PAM transmitter is combined with one frequency separated QAM transmitter.

Abstract: A transceiver according to the present invention receives data from a plurality of frequency separated transmission channels from a complementary transmitter and includes an interference filter for correcting for interference from transmitters other than the complementary transmitter. The interference filter, for example, can correct for near-end cross-talk and echo interference filtering and/or far-end crosstalk interference filtering is presented. A transceiver can include a transmitter portion and a receiver portion with one or more receivers coupled to receives signals in the plurality of frequency separated transmission channels. A baseband transmitter can be combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands).

Abstract: There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo canceller impedance model circuit is coupled to an output of the line driver and is coupled to an input of the line receiver. The echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents signal echoes that are present in the analog receive signals. The echo canceller impedance model circuit has a variable impedance for generating the echo canceller current. The variable impedance has at least one variable resistor and at least one variable capacitor.

Abstract: A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels.

Abstract: A receiver for a multi-channel system such as a HDMI system is presented. In accordance with the present invention, the receiver receives one of the plurality of channels and includes an analog portion, a digital-to-analog converter, and a digital control block that provides digital control signals to the analog portion. Equalization can be accomplished partially or wholly in the analog domain and digitally controlled by a digital control loop. A digital equalizer can also be included. A decision feedback equalizer can be implemented that sums an analog output signal into the analog data stream. Timing recovery can be accomplished by digital control of a phase interpolator or delay locked loop that receives a plurality of phases from a timing circuit coupled to receive a clock signal.

Abstract: A receiver system suitable for a local area network contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605). A symbol-information-carrying input analog signal (yk), or a first intermediate analog signal generated from the input analog signal, is filtered by filtering circuitry in the pre-filter to produce a filtered analog signal (Zs) with reduced intersymbol interference. The filtering circuitry operates according to a transfer function such as (b1s+1)/(a2s2+a1s+1) or (1?Vc)+VcPF(s) where Vc is adaptively varied. The analog-to-digital converter provides analog-to-digital signal conversion. The equalizer provides digital signal equalization to produce an equalized digital signal (a?k) as a stream of equalized digital values. The decoder converts the equalized digital values, or intermediate digital values generated from the equalized digital values, into a stream of symbols.