Abstract: A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels. A transmitter system and a receiver system are described for the communication system.

Abstract: A receiver for a multi-channel system such as a HDMI system is presented. In accordance with the present invention, the receiver receives one of the plurality of channels and includes an analog portion, a digital-to-analog converter, and a digital control block that provides digital control signals to the analog portion. Equalization can be accomplished partially or wholly in the analog domain and digitally controlled by a digital control loop. A digital equalizer can also be included. A decision feedback equalizer can be implemented that sums an analog output signal into the analog data stream. Timing recovery can be accomplished by digital control of a phase interpolator or delay locked loop that receives a plurality of phases from a timing circuit coupled to receive a clock signal.

Abstract: A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels. A transmitter system and a receiver system are described for the communication system.

Abstract: A sequence detector (1400-w) operating generally according to the Viterbi algorithm contains a branch metric generator (1402-w), comparison circuitry (1403-w), and symbol generation circuitry (1404, 1405, and 1406) for converting digital values of a detector input signal into a sequence of predefined symbols chosen from an alphabet of predefined symbols. The comparison circuitry provides soft output signals for correcting errors. The soft output signals include best and second-best state metrics (pk,w(i) and p2k,w(i)) and corresponding best and second-best comparison results (Dk,w(i) and D2k,w(i)). The symbol generation circuitry typically utilizes the best comparison results to generate a preliminary sequence of the predefined symbols, checks for error in the preliminary sequence, and utilizes the second-best comparison results in correcting any such error in the preliminary sequence so as to convert it into a final sequence of the predefined symbols.

Abstract: A sequence detector (1600-w) operating generally according to the Viterbi algorithm uses state reduction via division into symbol families to reduce the complexity of sequence detection. The sequence detector contains a branch metric generator (1402-w), comparison circuitry (1603-w), and symbol generation circuitry (1604, 1605-w, and 1606) for converting digital values of an input signal into a sequence of symbols chosen from an alphabet of predefined symbols allocated into multiple non-overlapping families each formed with a plurality of the predefined symbols. The branch metric generator makes intra-family branch selections, each of which is one of a plurality of branches respectively corresponding to a family's symbols, and generates corresponding branch metrics. The comparison circuitry determines state metrics and generates corresponding comparison results.

Abstract: There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo canceller impedance model circuit is coupled to an output of the line driver and is coupled to an input of the line receiver. The echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents signal echoes that are present in the analog receive signals. The echo canceller impedance model circuit has a variable impedance for generating the echo canceller current. The variable impedance has at least one variable resistor and at least one variable capacitor.

Abstract: A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels.

Abstract: A receiver for a multi-channel system such as a HDMI system is presented. In accordance with the present invention, the receiver receives one of the plurality of channels and includes an analog portion, a digital-to-analog converter, and a digital control block that provides digital control signals to the analog portion. Equalization can be accomplished partially or wholly in the analog domain and digitally controlled by a digital control loop. A digital equalizer can also be included. A decision feedback equalizer can be implemented that sums an analog output signal into the analog data stream. Timing recovery can be accomplished by digital control of a phase interpolator or delay locked loop that receives a plurality of phases from a timing circuit coupled to receive a clock signal.

Abstract: A detector system for high-speed Ethernet LAN is described. One embodiment includes a detector system having N one dimensional sequence detector equalizers in combination with an N-dimensional traceback decoder. The detector system detects N-dimensional symbols transmitted over N separate transport channels to N one-dimensional receivers. In one embodiment, Gigabit Ethernet receiver includes a four-wire transport to four 1D receivers and a 4D detector. The 4D detector in one embodiment is a parity code detector. In another embodiment, the 4D detector is a 4D trellis code detector.

Abstract: There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo canceller impedance model circuit is coupled to an output of the line driver and is coupled to an input of the line receiver. The echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents signal echoes that are present in the analog receive signals. The echo canceller impedance model circuit has a variable impedance for generating the echo canceller current. The variable impedance has at least one variable resistor and at least one variable capacitor.

Abstract: A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels.