Patents by Inventor Sreenath Unnikrishnan

Sreenath Unnikrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Body contact silicon-on-insulator transistor and method
    Publication number: 20030111693
    Abstract: A method for fabricating a body contact silicon-on-insulator transistor (10) includes forming a semiconductor substrate (12) over an insulator (14) and lightly doping the semiconductor substrate (12) to form a body region (18). The method also includes forming a gate (20) over the semiconductor substrate (12) and separated from the semiconductor substrate (12) by a gate insulator layer (21). The gate (20) defines a source region (22), a drain region (24) and a contact region (26). The method also includes masking a portion (36) of the gate (20) and the contact region (26) and heavily doping the source region (22), the drain region (24) and an unmasked portion (36) of the gate (20) with a material having a conductivity substantially opposite a conductivity of the body region (18).
    Type: Application
    Filed: January 28, 2003
    Publication date: June 19, 2003
    Inventor: Sreenath Unnikrishnan
  • Hydrogen anneal before gate oxidation
    Patent number: 6569741
    Abstract: A process for preparing a silicon surface for gate dielectric formation. The silicon is annealed in a hydrogen ambient prior to gate dielectric formation. The gate dielectric is then formed, along with other layers of the gate structure. The channel is then implanted with an ion implant through the gate material.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: May 27, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Theodore W. Houston, Sreenath Unnikrishnan
  • Body contact silicon-on-insulator transistor and method
    Patent number: 6555446
    Abstract: A method for fabricating a body contact silicon-on-insulator transistor (10) includes forming a semiconductor substrate (12) over an insulator (14) and lightly doping the semiconductor substrate (12) to form a body region (18). The method also includes forming a gate (20) over the semiconductor substrate (12) and separated from the semiconductor substrate (12) by a gate insulator layer (21). The gate (20) defines a source region (22), a drain region (24) and a contact region (26). The method also includes masking a portion (36) of the gate (20) and the contact region (26) and heavily doping the source region (22), the drain region (24) and an unmasked portion (36) of the gate (20) with a material having a conductivity substantially opposite a conductivity of the body region (18).
    Type: Grant
    Filed: October 19, 2000
    Date of Patent: April 29, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Sreenath Unnikrishnan
  • Body-tied-to-source partially depleted SOI MOSFET
    Publication number: 20020050614
    Abstract: A silicon-on-oxide MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact with the body node.
    Type: Application
    Filed: November 27, 2001
    Publication date: May 2, 2002
    Inventor: Sreenath Unnikrishnan
  • Hydrogen anneal before gate oxidation
    Publication number: 20020036324
    Abstract: A process for preparing a silicon surface for gate dielectric formation. The silicon is annealed in a hydrogen ambient prior to gate dielectric formation. The gate dielectric is then formed, along with other layers of the gate structure. The channel is then implanted with an ion implant through the gate material.
    Type: Application
    Filed: September 21, 2001
    Publication date: March 28, 2002
    Inventors: Theodore W. Houston, Sreenath Unnikrishnan
  • Body-tied-to-source partially depleted SOI MOSFET
    Patent number: 6353245
    Abstract: A silicon-on-oxide MOS transistor is disclosed which has an implanted region on the source side of the gate electrode for making contact with the body node.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: March 5, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Sreenath Unnikrishnan
  • Integrated circuit and method
    Patent number: 6287924
    Abstract: Sidewall spacers extending above a silicon gate with the distance between the spacers exceeding the length of the gate are used to confine selective silicon growth of the gate and subsequent self-aligned silicidation.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: September 11, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Chih-Ping Chao, Ih-Chin Chen, Rick L. Wise, Katherine E. Violette, Sreenath Unnikrishnan