Abstract: An alkoxysilane is contacted with water and an inorganic acid to form a first composition. A zirconium alkoxide is contacted with an organic acid to form a second composition. One or more alkoxysilanes and an organic acid are contacted with a mixture of the first and second compositions to form a sol-gel composition, to which a photoinitiator is added. The sol-gel composition has a ratio of a number of moles of silicon to a number of moles of zirconium (nSi/nZr) ranging from about 2 to about 10. The sol-gel composition is applied on a substrate (e.g., an aluminum alloy substrate) multiple times to form multiple sol-gel layers, and at least one of the sol-gel layers is cured by UV radiation. The multiple sol-gel layers are then thermally cured.

Abstract: A corrosion-resistant coating on an aluminum-containing substrate such as an aluminum substrate, an aluminum alloy substrate (e.g., AA 2024, AA 6061, or AA7075), or other aluminum-containing substrate includes a corrosion inhibitor-incorporated Zn—Al layered double hydroxide (LDH) layer and a sol-gel layer. A zinc salt and a corrosion inhibitor (e.g., a salt of an oxyanion of a transition metal such as a vanadate) is dissolved to form a zinc-corrosion inhibitor solution, and the substrate is immersed in or otherwise contacted with the solution to form the corrosion inhibitor-incorporated Zn—Al LDH layer on the substrate. A sol-gel composition is applied on the corrosion inhibitor-incorporated Zn—Al LDH layer of the substrate to form a sol-gel layer, and the sol-gel layer is cured.

Abstract: A Zn—Al layered double hydroxide (LDH) composition is added to a solution including a corrosion inhibitor and stirred, and a precipitate of the solution is collected, washed, and dried to form a corrosion inhibiting material (CIM), in which the LDH composition is intercalated with the corrosion inhibitor. An inorganic CIM and/or an organic CIM may be formed. The organic CIM may be added to a sol-gel composition to form an organic CIM-containing sol-gel composition, and the inorganic CIM may be added to a sol-gel composition to form an inorganic CIM-containing sol-gel composition. Further, the organic CIM-containing sol-gel composition may be applied on a substrate (e.g., an aluminum alloy substrate) to form an organic CIM-containing sol-gel layer and cured by ultraviolet (UV) radiation, the inorganic CIM-containing sol-gel composition may be applied on the substrate to form an inorganic CIM-containing sol-gel layer and cured by UV radiation, and the sol-gel layers may be thermally cured.

Abstract: Pharmaceutical compositions comprising an antidiabetic agent as an active agent are provided. The present invention relates to pharmaceutical compositions comprising linagliptin or a pharmaceutically acceptable salt thereof as an active agent. The present invention also relates to process of preparation of pharmaceutical compositions comprising linagliptin or a pharmaceutically acceptable salt thereof. The present invention also relates to method of administering the compositions comprising linagliptin to a subject in need thereof.

Abstract: According to an aspect of the present invention, the communication between processors and peripheral controllers is provided using packets. In an embodiment, the access requests are specified according to a common format such that all the information required for performing each access request is included in a single packet and sent to the peripheral controller. The peripheral controller performs the access request on the external device and generates a response. According to another aspect, the packet format enables the peripheral controller to send responses, requests originating from the external devices and interrupt requests. According to yet another aspect, the packets from processors are first stored in a random access memory (RAM) and a DMA controller retrieves the packets and delivered to the respective peripheral controllers.

Abstract: In accordance with an aspect of the present invention, a corresponding list of muxes is maintained for each combination of a peripheral and a mux option. The list is then retrieved to program the required muxes to connect the communication paths from a peripheral on the corresponding mux option, based on which the list is retrieved. In an embodiment, the information is maintained in the form of a table, with each entry storing the data corresponding to a mux and mux option. The entries are linked by appropriate pointers to form the linked list.

Abstract: According to an aspect of the present invention, the communication between processors and peripheral controllers is provided using packets. In an embodiment, the access requests are specified according to a common format such that all the information required for performing each access request is included in a single packet and sent to the peripheral controller. The peripheral controller performs the access request on the external device and generates a response. According to another aspect, the packet format enables the peripheral controller to send responses, requests originating from the external devices and interrupt requests. According to yet another aspect, the packets from processors are first stored in a random access memory (RAM) and a DMA controller retrieves the packets and delivered to the respective peripheral controllers.

Abstract: In accordance with an aspect of the present invention, a corresponding list of muxes is maintained for each combination of a peripheral and a mux option. The list is then retrieved to program the required muxes to connect the communication paths from a peripheral on the corresponding mux option, based on which the list is retrieved. In an embodiment, the information is maintained in the form of a table, with each entry storing the data corresponding to a mux and mux option. The entries are linked by appropriate pointers to form the linked list.

Abstract: A system chip has many local blocks including processor cores, caches, and memory controllers. Each local block has a local sample-select mux that is controlled by a local selection control register. The mux selects from among hundreds of internal sample nodes in the local block, and can also pass through samples output by an upstream local block. The selected samples from local blocks are sent to a central on-chip logic analyzer that compares the samples to a maskable trigger value. When the trigger value is matched, a trigger state machine advances, and samples are stored into a central capture buffer. A user debugging the chip can later read out the central capture buffer at a slower speed. Thousands of internal nodes from local blocks can be selected for sampling, triggering, and debugging. Local blocks include valid bits in 64-bit-wide samples. Only valid samples are written to the capture buffer.

Abstract: A computer product, method, and apparatus for causing a computer to perform load operations in a particular way are disclosed. The computer is made to replace a load instruction at a particular location in a computer program instruction sequence with two instructions, an advanced load instruction and a load check instruction. The advanced load instruction is inserted into the instruction sequence up-stream from where the original load instruction was located, and may be inserted above store instructions. The load check instruction is inserted into the instruction sequence after the store instructions. An Advanced Load Address Table (ALAT) structure, containing physical address data and validity data for each non-speculative advanced load, is updated with data about each advanced load and each store instruction executed, and queried on execution of each load check instruction about whether or not a particular advanced load is safe to use.