Patents by Inventor Sreenivas Mandava

Sreenivas Mandava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques for Determining Victim Row Addresses in a Volatile Memory
    Publication number: 20160224262
    Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
    Type: Application
    Filed: January 19, 2016
    Publication date: August 4, 2016
    Applicant: INTEL CORPORATION
    Inventors: SREENIVAS MANDAVA, BRIAN S. MORRIS, SUNEETA SAH, ROY M. STEVENS, TED ROSSIN, MATHEW W. STEFANIW, JOHN H. CRAWFORD
  • Techniques for determining victim row addresses in a volatile memory
    Patent number: 9269436
    Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: February 23, 2016
    Assignee: INTEL CORPORATION
    Inventors: Sreenivas Mandava, Brian S. Morris, Suneeta Sah, Roy M. Stevens, Ted Rossin, Mathew W. Stefaniw, John H. Crawford
  • Techniques for Probabilistic Dynamic Random Access Memory Row Repair
    Publication number: 20140281206
    Abstract: Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.
    Type: Application
    Filed: December 18, 2013
    Publication date: September 18, 2014
    Inventors: John H. Crawford, Brian S. Morris, Sreenivas Mandava, Raj K. Ramanujan
  • Techniques for Determining Victim Row Addresses in a Volatile Memory
    Publication number: 20140281207
    Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.
    Type: Application
    Filed: December 18, 2013
    Publication date: September 18, 2014
    Inventors: Sreenivas Mandava, Brian S. Morris, Suneeta Sah, Roy M. Stevens, Ted Rossin, Mathew W. Stefaniw, John H. Crawford