Abstract: An apparatus and method are provided for simplifying a finite field division, including inputs for the initial condition signals a(x), b(x), and p(x), and providing at an output node the signal c(x), where c(x)=a(x)/b(x) without intermediate inverter circuitry for finding 1/b(x). A reference register initialized to b(x), and a divider register initialized to a(x). Both registers are manipulated in parallel by a logic circuit which responds to the contents of the reference register, converting its contents to 1.Claim By applying the same manipulations to the divider register, its contents are converted from a(x) to a(x)/b(x).One embodiment of a finite field divider according to the present invention is used to provide a single finite field division of a single set of values a(x), b(x) and p(x). Another embodiment processes continuous streams of a(x), b(x) and p(x) values, to provide a continuous stream of c(x) values delayed by a calculation time.

Abstract: Digital data is processed by quantizing the data to produce samples, each with a most significant bits and least significant bits with the least significant bits representing reliabilities, generating a parities from the most significant bits of the samples, generating weight functions corresponding to the parities on the basis of the number of times a reliability measure occurs, and producing a corrected stream of data with the weight functions and the corresponding parities.

Abstract: A finite field parallel multiplier in GF(q.sup.m) including a router for directing 2m-1 components in m groups of m single-component signal lines towards m computing circuits for performing multiply and add modulo-q. The router guides m components from a first finite field element along with an additional m-1 components generated from linear combinations of the m components of the first finite field element. Each of the computing circuits receives all of the components from the second finite field element and m components provided by one set of signal lines through the router. Each computing circuit generates a single component for the resultant finite field element. These resulting components may be input through a basis change circuit to obtain a result in the desired basis.