Patents by Inventor Sreenivasan K. Koduri

Sreenivasan K. Koduri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11887906
    Abstract: A die-wrapped packaged device includes at least one flexible substrate having a top side and a bottom side that has lead terminals, where the top side has outer positioned die bonding features coupled by traces to through-vias that couple through a thickness of the flexible substrate to the lead terminals. At least one die includes a substrate having a back side and a topside semiconductor surface including circuitry thereon having nodes coupled to bond pads. One of the sides of the die is mounted on the top side of the flexible circuit, and the flexible substrate has a sufficient length relative to the die so that the flexible substrate wraps to extend over at least two sidewalls of the die onto the top side of the flexible substrate so that the die bonding features contact the bond pads.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: January 30, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K. Koduri
  • Patent number: 11830793
    Abstract: In some examples, a device comprises an electronic component having multiple electrical connectors, the multiple electrical connectors configured to couple to a printed circuit board (PCB) and having a first footprint. The device also comprises a multi-lead adapter comprising multiple rows of leads arranged in parallel, the leads in the rows configured to couple to the electrical connectors of the electronic component and having a second footprint that has a different size than the first footprint.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: November 28, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sreenivasan K. Koduri, Abram M. Castro
  • Patent number: 11810843
    Abstract: A microelectronic device has a die with a first electrically conductive pillar, and a second electrically conductive pillar, mechanically coupled to the die. The microelectronic device includes a first electrically conductive extended head electrically coupled to the first pillar, and a second electrically conductive extended head electrically coupled to the second pillar. The first pillar and the second pillar have equal compositions of electrically conductive material, as a result of being formed concurrently. Similarly, the first extended head and the second extended head have equal compositions of electrically conductive material, as a result of being formed concurrently. The first extended head provides a bump pad, and the second extended head provides at least a portion of a first plate of an integrated capacitor. A second plate may be located in the die, between the first plate and the die, or on an opposite of the first plate from the die.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: November 7, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Patent number: 11797732
    Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: October 24, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ashish Khandelwal, Sreenivasan K. Koduri, Nikhil Gupta, Timothy W. Fischer
  • Publication number: 20230326913
    Abstract: In a described example, an apparatus includes: a first mold compound partially covering a thermal pad that extends through a pre-molded package substrate formed of a first mold compound, a portion of the thermal pad exposed on a die side surface of the pre-molded package substrate, the pre-molded package substrate having a recess on the die side surface, with an exposed portion of the thermal pad and a portion of the first mold compound in a die mounting area in the recess; a semiconductor die mounted to the thermal pad and another semiconductor die mounted to the mold compound in the die mounting area; wire bonds coupling bond pads on the semiconductor dies to traces on the pre-molded package substrate; and a second mold compound over the die side surface of the pre-molded package substrate and covering the wire bonds, the semiconductor dies, the recess, and a portion of the traces.
    Type: Application
    Filed: June 13, 2023
    Publication date: October 12, 2023
    Inventors: Sreenivasan K. Koduri, Steven R. Tom, Paul Brohlin
  • Publication number: 20230299027
    Abstract: A semiconductor packaging structure includes a die including a bond pad and a first metal layer structure disposed on the die, the first metal layer structure having a first width, the first metal layer structure including a first metal layer, the first metal layer electrically coupled to the bond pad. The semiconductor packaging structure also includes a first photosensitive material around sides of the first metal layer structure and a second metal layer structure disposed over the first metal layer structure and over a portion of the first photosensitive material, the second metal layer structure electrically coupled to the first metal layer structure, the second metal layer structure having a second width, where the second width is greater than the first width. Additionally, the semiconductor packaging structure includes a second photosensitive material around sides of the second metal layer structure.
    Type: Application
    Filed: May 26, 2023
    Publication date: September 21, 2023
    Inventor: Sreenivasan K. Koduri
  • Patent number: 11756914
    Abstract: A microelectronic device has a die with a die conductor at a connection surface. The microelectronic device includes a pillar electrically coupled to the die conductor, and a head electrically coupled to the pillar. The pillar has a die-side flared end at a die end of the pillar; the pillar widens progressively along the die-side flared end, and extends outward by more than a lesser of half a thickness of the die conductor and half a lateral width of the pillar midway between a die end and a head end. The pillar has a head-side flared end at a head end of the pillar; the pillar widens progressively along the die-side flared end, and extends outward by a distance that is greater than a lesser of half a thickness of the head and half the lateral width of the pillar. Methods of forming the microelectronic device are disclosed.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: September 12, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K. Koduri
  • Patent number: 11749616
    Abstract: A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: September 5, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K Koduri
  • Patent number: 11748533
    Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: September 5, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ashish Khandelwal, Sreenivasan K. Koduri, Nikhil Gupta, Timothy W. Fischer
  • Publication number: 20230260879
    Abstract: A packaged electronic device includes a package structure with opposite first and second sides spaced apart from one another along a first direction, and opposite third and fourth sides spaced apart from one another along a second direction, as well as first and second leads. The first lead includes a first portion that extends outward from the third side of the package structure and extends downward toward a plane of the first side and away from a plane of the second side. The second lead includes a first portion that extends outward from the third side of the package structure, and the second lead extends upward toward the plane of the second side and away from the plane of the first side to allow connection to another circuit or component, such as a second packaged electronic device, a passive circuit component, a printed circuit board, etc.
    Type: Application
    Filed: April 27, 2023
    Publication date: August 17, 2023
    Inventor: Sreenivasan K. Koduri
  • Patent number: 11727175
    Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: August 15, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy W. Fischer, Ashish Khandelwal, Sreenivasan K. Koduri, Nikhil Gupta
  • Publication number: 20230253443
    Abstract: A microelectronic device has bump bonds and an inductor on a die. The microelectronic device includes first lateral conductors extending along a terminal surface of the die, wherein at least some of the first lateral conductors contact at least some of terminals of the die. The microelectronic device also includes conductive columns on the first lateral conductors, extending perpendicularly from the terminal surface, and second lateral conductors on the conductive columns, opposite from the first lateral conductors, extending laterally in a plane parallel to the terminal surface. A first set of the first lateral conductors, the conductive columns, and the second lateral conductors provide the bump bonds of the microelectronic device. A second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form the inductor. Methods of forming the microelectronic device are also disclosed.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: Texas Instruments Incorporated
    Inventor: Sreenivasan K Koduri
  • Patent number: 11705414
    Abstract: A semiconductor packaging structure includes a die including a bond pad and a first metal layer structure disposed on the die, the first metal layer structure having a first width, the first metal layer structure including a first metal layer, the first metal layer electrically coupled to the bond pad. The semiconductor packaging structure also includes a first photosensitive material around sides of the first metal layer structure and a second metal layer structure disposed over the first metal layer structure and over a portion of the first photosensitive material, the second metal layer structure electrically coupled to the first metal layer structure, the second metal layer structure having a second width, where the second width is greater than the first width. Additionally, the semiconductor packaging structure includes a second photosensitive material around sides of the second metal layer structure.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: July 18, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K. Koduri
  • Patent number: 11694947
    Abstract: In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: July 4, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Sreenivasan K. Koduri, Nazila Dadvand
  • Patent number: 11682609
    Abstract: A packaged electronic device includes a package structure with opposite first and second sides spaced apart from one another along a first direction, and opposite third and fourth sides spaced apart from one another along a second direction, as well as first and second leads. The first lead includes a first portion that extends outward from the third side of the package structure and extends downward toward a plane of the first side and away from a plane of the second side. The second lead includes a first portion that extends outward from the third side of the package structure, and the second lead extends upward toward the plane of the second side and away from the plane of the first side to allow connection to another circuit or component, such as a second packaged electronic device, a passive circuit component, a printed circuit board, etc.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: June 20, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K. Koduri
  • Patent number: 11676884
    Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: June 13, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Michael Sutton, Sreenivasan K Koduri, Subhashish Mukherjee
  • Patent number: 11676951
    Abstract: In a described example, an apparatus includes: a first mold compound partially covering a thermal pad that extends through a pre-molded package substrate formed of a first mold compound, a portion of the thermal pad exposed on a die side surface of the pre-molded package substrate, the pre-molded package substrate having a recess on the die side surface, with an exposed portion of the thermal pad and a portion of the first mold compound in a die mounting area in the recess; a semiconductor die mounted to the thermal pad and another semiconductor die mounted to the mold compound in the die mounting area; wire bonds coupling bond pads on the semiconductor dies to traces on the pre-molded package substrate; and a second mold compound over the die side surface of the pre-molded package substrate and covering the wire bonds, the semiconductor dies, the recess, and a portion of the traces.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: June 13, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sreenivasan K. Koduri, Steven R. Tom, Paul Brohlin
  • Patent number: 11640968
    Abstract: A microelectronic device has bump bonds and an inductor on a die. The microelectronic device includes first lateral conductors extending along a terminal surface of the die, wherein at least some of the first lateral conductors contact at least some of terminals of the die. The microelectronic device also includes conductive columns on the first lateral conductors, extending perpendicularly from the terminal surface, and second lateral conductors on the conductive columns, opposite from the first lateral conductors, extending laterally in a plane parallel to the terminal surface. A first set of the first lateral conductors, the conductive columns, and the second lateral conductors provide the bump bonds of the microelectronic device. A second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form the inductor. Methods of forming the microelectronic device are also disclosed.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: May 2, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K Koduri
  • Patent number: 11636242
    Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: April 25, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ashish Khandelwal, Sreenivasan K. Koduri, Nikhil Gupta, Timothy W. Fischer
  • Publication number: 20230055211
    Abstract: An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Applicant: Texas Instruments Incorporated
    Inventors: Sylvester Ankamah-Kusi, Yiqi Tang, Rajen Manicon Murugan, Sreenivasan K. Koduri