Patents by Inventor Sreenivasan K. Koduri

Sreenivasan K. Koduri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210143106
    Abstract: In a described example, an apparatus includes a packaged device carrier having a board side surface and an opposing surface, the packaged device carrier having conductive leads having a first thickness spaced from one another; the conductive leads having a head portion attached to a dielectric portion, a middle portion extending from the head portion and extending away from the board side surface of the packaged device carrier at an angle to the opposing surface, and each lead having an end extending from the middle portion with a foot portion configured for mounting to a substrate.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 13, 2021
    Inventor: Sreenivasan K. Koduri
  • Patent number: 10991641
    Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: April 27, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Michael Sutton, Sreenivasan K Koduri, Subhashish Mukherjee
  • Patent number: 10985096
    Abstract: In described examples, a terminal (e.g., a conductive terminal) includes a base material, a plating stack and a solder finish. The base material can be a metal, such as copper. The plating stack is arranged on a surface of the base material, and includes breaks in the plating stack. The breaks in the plating stack extend from a first surface of the plating stack to a second surface of the plating stack adjacent to the surface of the base material. The solder finish is coated over the breaks in the plating stack.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: April 20, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20210100108
    Abstract: A microelectronic device includes a die less than 300 microns thick, and an interface tile. Die attach leads on the interface tile are electrically coupled to die terminals on the die through interface bonds. The microelectronic device includes an interposer between the die and the interface tile. Lateral perimeters of the die, the interposer, and the interface tile are aligned with each other. The microelectronic device may be formed by forming the interface bonds and an interposer layer, while the die is part of a wafer and the interface tile is part of an interface lamina. Kerfs are formed through the interface lamina, through the interposer, and partway through the wafer, around a lateral perimeter of the die. Material is subsequently removed at a back surface of the die to the kerfs, so that a thickness of the die is less than 300 microns.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 1, 2021
    Applicant: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20210098348
    Abstract: A microelectronic device has a die with a first electrically conductive pillar, and a second electrically conductive pillar, mechanically coupled to the die. The microelectronic device includes a first electrically conductive extended head electrically coupled to the first pillar, and a second electrically conductive extended head electrically coupled to the second pillar. The first pillar and the second pillar have equal compositions of electrically conductive material, as a result of being formed concurrently. Similarly, the first extended head and the second extended head have equal compositions of electrically conductive material, as a result of being formed concurrently. The first extended head provides a bump pad, and the second extended head provides at least a portion of a first plate of an integrated capacitor. A second plate may be located in the die, between the first plate and the die, or on an opposite of the first plate from the die.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 1, 2021
    Applicant: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20210098406
    Abstract: A microelectronic device has a die with a die conductor at a connection surface. The microelectronic device includes a pillar electrically coupled to the die conductor, and a head electrically coupled to the pillar. The pillar has a die-side flared end at a die end of the pillar; the pillar widens progressively along the die-side flared end, and extends outward by more than a lesser of half a thickness of the die conductor and half a lateral width of the pillar midway between a die end and a head end. The pillar has a head-side flared end at a head end of the pillar; the pillar widens progressively along the die-side flared end, and extends outward by a distance that is greater than a lesser of half a thickness of the head and half the lateral width of the pillar. Methods of forming the microelectronic device are disclosed.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 1, 2021
    Applicant: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Patent number: 10957666
    Abstract: In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The semiconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: March 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20210050287
    Abstract: In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Inventors: Sreenivasan K. KODURI, Nazila DADVAND
  • Publication number: 20210013116
    Abstract: A die-wrapped packaged device includes at least one flexible substrate having a top side and a bottom side that has lead terminals, where the top side has outer positioned die bonding features coupled by traces to through-vias that couple through a thickness of the flexible substrate to the lead terminals. At least one die includes a substrate having a back side and a topside semiconductor surface including circuitry thereon having nodes coupled to bond pads. One of the sides of the die is mounted on the top side of the flexible circuit, and the flexible substrate has a sufficient length relative to the die so that the flexible substrate wraps to extend over at least two sidewalls of the die onto the top side of the flexible substrate so that the die bonding features contact the bond pads.
    Type: Application
    Filed: July 9, 2019
    Publication date: January 14, 2021
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20200411420
    Abstract: A packaged electronic device includes a package structure with opposite first and second sides spaced apart from one another along a first direction, and opposite third and fourth sides spaced apart from one another along a second direction, as well as first and second leads. The first lead includes a first portion that extends outward from the third side of the package structure and extends downward toward a plane of the first side and away from a plane of the second side. The second lead includes a first portion that extends outward from the third side of the package structure, and the second lead extends upward toward the plane of the second side and away from the plane of the first side to allow connection to another circuit or component, such as a second packaged electronic device, a passive circuit component, a printed circuit board, etc.
    Type: Application
    Filed: June 29, 2019
    Publication date: December 31, 2020
    Applicant: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20200411416
    Abstract: A method of making a semiconductor package includes providing a base made from a conductive material. A surface of the base is covered with an outer layer of material different from the conductive material. Gaps are formed in the outer layer. The base is etched through the gaps to form projections on the base extending along a centerline to an end surface. Each projection has a first width at the end surface and a second width at the base less than the first width. The outer layer is removed. Leads and a die pad are formed from the base with the projections extending from the leads and the die pad. A die is attached to the projections. An insulating layer is provided over the leads, the die, and the die pad.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Sreenivasan K. Koduri, Sylvester Ankamah-Kusi
  • Patent number: 10840171
    Abstract: A packaged semiconductor device includes a semiconductor die mounted on a leadframe, a housing for the semiconductor die defining a horizontal plane and a horizontal direction. The leadframe includes leads each having an inner lead portion inside the housing and an outer lead portion that includes a first portion that extends out in the horizontal direction from one of the sidewalls of the housing, a transition portion that includes a vertical direction component, and a distal end portion, wherein the distal end portion of the leads are all on the horizontal plane. The outer lead portions alternate between a gull wing lead shape having the distal end portions extending in the horizontal direction outward from the housing and inward extending leads that have their distal end portions extending in the horizontal direction inward toward the housing. The leadframe consists of a single leadframe.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael L. Meyers, Scott F. Eisenhart, Richard J. Saye, Sreenivasan K. Koduri
  • Publication number: 20200343165
    Abstract: In some examples, a device comprises an electronic component having multiple electrical connectors, the multiple electrical connectors configured to couple to a printed circuit board (PCB) and having a first footprint. The device also comprises a multi-lead adapter comprising multiple rows of leads arranged in parallel, the leads in the rows configured to couple to the electrical connectors of the electronic component and having a second footprint that has a different size than the first footprint.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Inventors: Sreenivasan K. KODURI, Abram M. CASTRO
  • Publication number: 20200279800
    Abstract: In described examples, a terminal (e.g., a conductive terminal) includes a base material, a plating stack and a solder finish. The base material can be a metal, such as copper. The plating stack is arranged on a surface of the base material, and includes breaks in the plating stack. The breaks in the plating stack extend from a first surface of the plating stack to a second surface of the plating stack adjacent to the surface of the base material. The solder finish is coated over the breaks in the plating stack.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20200266131
    Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventors: Benjamin Michael Sutton, Sreenivasan K. Koduri, Subhashish Mukherjee
  • Publication number: 20200258856
    Abstract: A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.
    Type: Application
    Filed: April 28, 2020
    Publication date: August 13, 2020
    Inventor: Sreenivasan K. Koduri
  • Patent number: 10734313
    Abstract: A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Morroni, Rajeev Dinkar Joshi, Sreenivasan K. Koduri, Sujan Kundapur Manohar, Yogesh K. Ramadass, Anindya Poddar
  • Publication number: 20200203242
    Abstract: A microelectronic device, in a fan-out fan-in chip scale package, has a die and an encapsulation material at least partially surrounding the die. Fan-out connections from the die extend through the encapsulation material and terminate adjacent to the die. The fan-out connections include wire bonds, and are free of photolithographically-defined structures. Fan-in/out traces connect the fan-out connections to bump bond pads. The die and at least a portion of the bump bond pads partially overlap each other. The microelectronic device is formed by mounting the die on a carrier, and forming the fan-out connections, including the wire bonds, without using a photolithographic process. The die and the fan-out connections are covered with an encapsulation material, and the carrier is subsequently removed, exposing the fan-out connections. The fan-in/out traces are formed so as to connect to the exposed portions of the fan-out connections, and extend to the bump bond pads.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Applicant: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20200203243
    Abstract: A microelectronic device, in a leaded/leadless chip scale package, has a die and intermediate pads located adjacent to the die. The intermediate pads are free of photolithographically-defined structures. Wire bonds connect the die to the intermediate pads. An encapsulation material at least partially surrounds the die and the wire bonds, and contacts the intermediate pads. Package leads, located outside of the encapsulation material, are attached to the intermediate pads. The microelectronic device is formed by mounting the die on a carrier, and forming the intermediate pads on the carrier without using a photolithographic process. Wire bonds are formed between the die and the intermediate pads. The die, the wire bonds, and the intermediate pads are covered with an encapsulation material, and the carrier is subsequently removed, exposing the intermediate pads. The package leads are attached to the intermediate pads.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Applicant: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri
  • Publication number: 20200203263
    Abstract: A microelectronic device, in a fan-out chip scale package, has a die and an encapsulation material at least partially surrounding the die. The microelectronic device includes bump bond pads adjacent to the die that are exposed by the encapsulation material, the bump bond pads being free of photolithographically-defined structures. Wire bonds connect the die to the bump bond pads. The microelectronic device is formed by mounting the die on a carrier, and forming the bump bond pads adjacent to the die without using a photolithographic process. Wire bonds are formed between the die and the bump bond pads. The die, the wire bonds, and the bump bond pads are covered with an encapsulation material, and the carrier is subsequently removed, exposing the bump bond pads.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Applicant: Texas Instruments Incorporated
    Inventor: Sreenivasan K. Koduri