Patents by Inventor Sreenivasan Kalyani Koduri
Sreenivasan Kalyani Koduri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12062597Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.Type: GrantFiled: April 10, 2023Date of Patent: August 13, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Christopher Daniel Manack, Sreenivasan Kalyani Koduri
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Publication number: 20240243024Abstract: In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.Type: ApplicationFiled: March 27, 2024Publication date: July 18, 2024Inventors: Sreenivasan Kalyani Koduri, Leslie Edward Stark, Steven Alfred KummerlL, Wai Lee
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Publication number: 20240178184Abstract: A packaged integrated circuit (IC), comprising: a lead frame; one or more semiconductor dies on the lead frame, the one or more semiconductor dies including a first circuit and a second circuit; and a molding compound encapsulating the lead frame and the semiconductor die, the molding compound including a first cavity over the first circuit and a second cavity over the second circuit, in which at least one of the first or second cavities includes a second material different from the molding compound.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Applicant: Texas Instruments IncorporatedInventors: Sreenivasan Kalyani KODURI, Leslie Edward STARK
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Patent number: 11972994Abstract: In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.Type: GrantFiled: April 12, 2023Date of Patent: April 30, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sreenivasan Kalyani Koduri, Leslie Edward Stark, Steven Alfred Kummerl, Wai Lee
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Patent number: 11894339Abstract: A method of manufacturing a sensor device includes obtaining a semiconductor die structure comprising a transmitter and a receiver. Then, a first sacrificial stud is affixed to the transmitter and a second sacrificial stud is affixed to the receiver. The semiconductor die is affixed to a lead frame, and pads on the semiconductor die structure are wirebonded to the lead frame. The lead frame, the semiconductor die structure, and the wirebonds are encapsulated in a molding compound, while the tops of the first and second sacrificial studs are left exposed. The first and second sacrificial studs prevent the molding compound from encapsulating the transmitter and the receiver, and are removed to expose the transmitter in a first cavity and the receiver in a second cavity. In some examples, the semiconductor die structure includes a first semiconductor die comprising the transmitter and a second semiconductor die comprising the receiver.Type: GrantFiled: December 14, 2020Date of Patent: February 6, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sreenivasan Kalyani Koduri, Leslie Edward Stark
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Publication number: 20240038609Abstract: In some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. The cover comprises a monolithic structure including a vertical portion and a horizontal portion. A hollow area is between the cover and the operational component. The package also includes a mold compound covering the semiconductor die and the cover.Type: ApplicationFiled: October 10, 2023Publication date: February 1, 2024Inventors: Sreenivasan Kalyani KODURI, Leslie Edward STARK
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Patent number: 11869864Abstract: In some examples, a system comprises a set of nanoparticles and a set of nanowires extending from the set of nanoparticles.Type: GrantFiled: February 24, 2022Date of Patent: January 9, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Ralf Muenster, Sreenivasan Kalyani Koduri
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Patent number: 11869820Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.Type: GrantFiled: July 1, 2022Date of Patent: January 9, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Amit Sureshkumar Nangia, Sreenivasan Kalyani Koduri, Siva Prakash Gurrum, Christopher Daniel Manack
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Publication number: 20230352373Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.Type: ApplicationFiled: April 10, 2023Publication date: November 2, 2023Inventors: Christopher Daniel Manack, Sreenivasan Kalyani Koduri
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Patent number: 11791296Abstract: In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.Type: GrantFiled: December 7, 2021Date of Patent: October 17, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Scott Robert Summerfelt, Benjamin Stassen Cook, Ralf Jakobskrueger Muenster, Sreenivasan Kalyani Koduri
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Patent number: 11791248Abstract: In examples, a semiconductor device comprises a semiconductor die, an opaque mold compound housing covering the semiconductor die, a conductive terminal extending from the mold compound housing, and an insulative coat covering the mold compound housing and at least a portion of the conductive terminal.Type: GrantFiled: January 10, 2023Date of Patent: October 17, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Sreenivasan Kalyani Koduri
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Patent number: 11784103Abstract: In some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. The cover comprises a monolithic structure including a vertical portion and a horizontal portion. A hollow area is between the cover and the operational component. The package also includes a mold compound covering the semiconductor die and the cover.Type: GrantFiled: December 9, 2020Date of Patent: October 10, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sreenivasan Kalyani Koduri, Leslie Edward Stark
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Patent number: 11728242Abstract: In some examples, a semiconductor package comprises a semiconductor die having a first surface and a second surface opposing the first surface. The package comprises an orifice extending through a thickness of the semiconductor die from the first surface to the second surface. The package comprises a set of metallic nanowires positioned within the orifice and extending through the thickness of the semiconductor die from the first surface to the second surface.Type: GrantFiled: April 8, 2020Date of Patent: August 15, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Ralf Jakobskrueger Muenster, Sreenivasan Kalyani Koduri
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Publication number: 20230253277Abstract: In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.Type: ApplicationFiled: April 12, 2023Publication date: August 10, 2023Inventors: Sreenivasan Kalyani KODURI, Leslie Edward STARK, Steven Alfred KUMMERL, Wai LEE
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Patent number: 11714011Abstract: A system comprises a member to receive a mechanical force, and a sensor to sense the mechanical force. The sensor is mounted on the member using a set of nanoparticles and a set of nanowires coupled to the set of nanoparticles.Type: GrantFiled: April 8, 2020Date of Patent: August 1, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ralf Jakobskrueger Muenster, Sreenivasan Kalyani Koduri, Benjamin Stassen Cook
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Patent number: 11658083Abstract: In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.Type: GrantFiled: December 9, 2020Date of Patent: May 23, 2023Assignee: Texas Instruments IncorporatedInventors: Sreenivasan Kalyani Koduri, Leslie Edward Stark, Steven Alfred Kummerl, Wai Lee
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Patent number: 11631632Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.Type: GrantFiled: December 28, 2020Date of Patent: April 18, 2023Assignee: Texas Instruments IncorporatedInventors: Christopher Daniel Manack, Sreenivasan Kalyani Koduri
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Publication number: 20230030266Abstract: In examples, a sensor package includes a semiconductor die, a sensor on the semiconductor die, and a mold compound covering the semiconductor die. The mold compound includes a sensor cavity over the sensor. The sensor package includes a polymer film member on the sensor and circumscribed by a wall of the mold compound forming the sensor cavity. The polymer film member is exposed to an exterior environment of the sensor package.Type: ApplicationFiled: September 30, 2022Publication date: February 2, 2023Inventors: Sreenivasan Kalyani KODURI, Leslie Edward STARK
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Patent number: 11552006Abstract: In examples, a semiconductor device comprises a semiconductor die, an opaque mold compound housing covering the semiconductor die, a conductive terminal extending from the mold compound housing, and an insulative coat covering the mold compound housing and at least a portion of the conductive terminal.Type: GrantFiled: July 22, 2020Date of Patent: January 10, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Sreenivasan Kalyani Koduri
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Publication number: 20220336304Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Inventors: Amit Sureshkumar Nangia, Sreenivasan Kalyani Koduri, Siva Prakash Gurrum, Christopher Daniel Manack